View ST7267C8_382394.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ST7267
USB 2.0 HIGH SPEED MASS STORAGE MICROCONTROLLER
PRELIMINARY DATA

USB 2.0 Interface compliant with Mass Storage Device Class - Integrated USB 2.0 PHY - Supports USB High Speed and Full Speed - 1 control endpoint with two 64-byte buffers - 1 IN 64-byte bulk / interrupt endpoint - 1 OUT 64-byte bulk / interrupt endpoint - 1 IN 512-byte double buffer bulk endpoint - 1 OUT 512-byte double buffer bulk endpoint - Suspend and Resume operations Mass Storage Controller Interface (MSCI) - 16-bit RISC Core - Supports all types of NAND Flash devices - Reed-Solomon Encoder/Decoder for MLC NAND Flash support: on-the-fly correction (4 bytes of a 512-byte block) Memories - 54K of ROM - 4 Kbytes of RAM with up to 256 bytes stack - 2 Kbytes of MSCI CODE RAM - 5 Kbytes of dual-ported RAM Embedded 8-bit ST7 MCU Supply Management - 3.3V operation - Integrated 3.3V-1.8V voltage regulator Clock Management - Integrated PLL for generating core and USB 2.0 clock sources using an external 12 MHz crystal
TQFP48 7x7
TQFP64 10x10

Interrupt Management - 11 Interrupt vectors plus TRAP and RESET - 40 I/Os interrupt source mapped on 5 vectors - Nested interrupt management I/O Ports - Up to 40 general purpose I/O port pins - Two 5V tolerant I/Os Communication Interface - 1 SPI Synchronous serial interface Timers - Configurable Watchdog for system reliability - 16-bit timer - Time Base Unit TQFP48 7x7 and TQFP64 10x10 lead-free packages Development Support - Complete reference design including BOM and gerber files - Supports Windows ME, Windows 2K, Windows XP. Drivers available for Windows SE - Complete application package available to design a USB 2.0 Flash Drive application
ST7267R8
Features Program memory User RAM (stack) - bytes Peripherals USB interface # of NAND devices supported Operating Supply Operating Temperature Packages
ST7267C8 54K 4K (256) WDG, TBU, Timer, SPI, MSCI USB 2.0 4 2.7V to 3.6V 0C to +70C TQFP48 7x7
TQFP64 10x10
Rev. 1
October 2005 1/186
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 ST7 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 PAGED MEMORY SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 INTERRUPT AND VECTOR REMAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 ST7 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 ST7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.1 HALT MODE RECOMMENDATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 ST7 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 ST7 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 29 29 32
6.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 ST7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.5 INTERRUPT VECTOR TABLE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.6.1 Software and Hardware Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.2 Enable and Sensitivity Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.3 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 42
8 ST7 CLOCK, RESET AND SUPPLY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2 CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.2.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 186 8.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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8.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.4 Illegal Opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 SUPPLY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 53 53 54
9 ST7 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10 ST7 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.4 Generating a Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.5 Software Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.7 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.8 Using Halt Mode with the WDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.10 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 TIMEBASE UNIT (TBU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.4 Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 USB INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.1 10.5.2 10.5.3 10.5.4 10.5.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB2.0 PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 56 56 57 57 57 57 58 58 58 59 59 59 59 59 60 60 60 62 62 62 62 74 74 74 75 81 81 81 81 86 87 89 89 90 93 93 93 93 94 94
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10.5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.5.7 Programming consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.5.8 USB reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.5.9 Suspend /Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.5.10 Endpoint 0 handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.5.11 Bulk IN Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.5.12 Bulk OUT Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.5.13 Interrupt IN Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.5.14 Interrupt OUT endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.5.15 Low Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 10.5.16 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 10.5.17 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11 MASS STORAGE COMMUNICATION INTERFACE (MSCI) . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12 MSCI REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13 MSCI CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14 MSCI ST7 INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 14.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 14.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 14.2.1 ST7 Control of the MSCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.2 Interrupt generation from MSCI to ST7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3 Program RAM upload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.4 ST7 Write Access to MSCI Code RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.5 Example Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6 ST7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.7 Low Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MSCI I/O CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1 Input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2 Output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 I/O SHARING BETWEEN ST7 AND MSCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 116 116 117 118 119 121 121 123 123 123 123 123 124
15.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
15.3.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 16 MSCI VCI INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 16.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 16.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 16.3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 16.4 ERROR MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 16.4.1 MSCI VCI Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 129 ... 16.4.2 MSCI VCI Interface software example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 16.5 USB REGISTER ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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17 MSCI PARALLEL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 17.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 17.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 17.2.1 FIFO management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 17.3 CONFIGURING THE CONTROL LINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 17.3.1 Control Signal Enable bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 17.3.2 Control Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 17.4 MSCI PARALLEL INTERFACE CONFIGURATION EXAMPLES . . . . . . . . . . . . . . . . . . 145 17.4.1 Examples for output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 17.4.2 Examples for input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 17.5 CASE OF NON CONTINUOUS DATA FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 17.5.1 Double buffer underflow in output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 17.5.2 Double buffer overflow in input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 17.6 ECC GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 17.7 REED SOLOMON ENCODER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 17.8 REED SOLOMON DECODER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 17.9 MSCI SOFTWARE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 17.9.1 Loop for data send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 17.9.2 Loop for data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 17.10REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 18 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 18.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 18.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 161 161 161 161 162 162 162 162 163
18.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 18.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 18.4.1 RUN and WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.2 HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.3 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 164 164 165
18.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 18.5.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 18.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 18.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 18.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 18.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 167 18.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
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18.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . 168 18.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 18.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 18.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 18.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 18.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 18.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 18.10.1 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.10.2 Time Base Unit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.10.3 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.11OTHER COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . 18.11.1 MSCI Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.11.2 USB (Universal Bus Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.11.3 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 174 174 175 175 176 178 180 180
19.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 20 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 182 20.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 21 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . . . . . 183 22 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
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1 INTRODUCTION
The ST7267 is a USB 2.0 highspeed Mass Storage microcontroller. The USB 2.0 highspeed interface including PHY and function supports USB 2.0 Mass Storage Device Class. The Mass Storage Controller Interface (MSCI) features a 16-bit RISC ALU core combined with the Reed-Solomon Encoder/Decoder on-the-fly correction on 512 data byte blocks provides a flexible, high transfer rate solution for interfacing all types of NAND Flash memory devices. The internal 60 MHz PLL driven by the 12 MHz oscillator is used to generate the 480 MHz frequency for the USB 2.0 PHY. The ST7 CPU runs the application program from the internal ROM and RAM. USB data and patch code are stored in internal RAM. The I/O ports provide functions for EEPROM connection, LEDs and write protect switch control. The internal 3.3V to 1.8V voltage regulator provides the 1.8V supply voltage to the digital part of the circuit. 1.1 RELATED DOCUMENTATION For details on the programming model of the ST7 CPU and the MSCI, please refer to the following manuals: Mass Storage Controller Interface MSCI 16-bit Core Programming Manual ST7 Programming Manual
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INTRODUCTION (Cont'd) Figure 1. Device Block Diagram
1.8V core supply
VDD33 VSS33
5 5
POWER SUPPLY REGULATOR
MSCIcoreclk Clock MSCIperiphclk Generator CPUclk
PLL 60MHz USBrefclk TBU PORT E SPI PORT D TIMER PORT C PORT B PORT A
12MHz OSC
VDDOUSB
1.8V USB supply
OSCOUT OSCIN VSSA VDDA
WATCHDOG ST7 8 -BIT ALU CORE 16-BIT ADDRESS AND 8-BIT DATA BUS TST/CONTROL
RESET
PE[7:0] (8 bits)
PD[7:0] (8 bits) PC[7:0] (8 bits) PB[7:0] (8 bits) PA[7:0] (8 bits) USBDM, USBDP USB2.0 PHY VSSBL, VDDBL VSSC,VDDC VDD3 RREF
ST7 ROM 54 KBytes
ST7 DATA RAM 4224B
ST7 CPU
USB FUNCTION VCI I/F RAM I/F
DUAL-PORTED RAM 5 KB DPRAM MSCI CODE SRAM 2 KBytes ST7 Interface
Vci Access Control
USBrefclk USB BUFFER RAM 2304 Bytes
VCI Interface REGISTER BUS MSCI 16-BIT ALU CORE
RAM 512 Bytes RS
Parallel Solomon Interface. ECC Port 1
Reed-
MSCIcoreclk
MASS STORAGE COMMUNICATION INTERFACE
I/O Controller
Port 2 MSCIperiphclk
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2 PIN DESCRIPTION
Figure 2. 48-Pin TQFP Package Pinout
VDDA OSCIN OSCOUT VSSA RREF VSSC VDDC VDD3 USBDP USBDM VSSBL VDDBL
48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDDOUSB VSS_4 VDD33_4 MSCIP2[7] / PC7 MSCIP2[6] / PC6 MSCIP2[5] / PC5 MSCIP2[4] / PC4 MSCIP2[3] / PC3 MSCIP2[2] / PC2 MSCIP2[1] / PC1 PE0 VDD33_3
VSS_1 VDD33_1
PE1 PA0 / MSCIP1[0] PA1 / MSCIP1[1] PA2 / MSCIP1[2] PA3 / MSCIP1[3] PA4 / MSCIP1[4] PA5 / MSCIP1[5] PA6 / MSCIP1[6] PA7 / MSCIP1[7] PD0 / MSCIP2[8]
PD1 / MSCIP2[1] PD2 / MSCIP2[2] PD3 / MSCIP2[3] VSS_2 VDD33_2 PD4 / MSCIP2[4] PE7 RESET PE2 / ICC_DATA PE3 / ICC_CLK PC0 / MSCIP2[0] VSS_3
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PIN DESCRIPTION (Cont'd) Figure 3. 64-Pin TQFP Package Pinout
MSCIP1[13] / PB5 MSCIP1[12] / PB4 MSCIP1[11] / PB3 MSCIP1[10] / PB2 VDDA OSCIN OSCOUT VSSA RREF VSSC VDDC VDD3 USBDP USBDM VSSBL VDDBL
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDDOUSB VSS_4 VDD33_4 MSCIP1[9] / PB1 MSCIP1[8] / PB0 MSCIP2[7] / TICP1 / PC7 MSCIP2[6] / TOCP1 / PC6 MSCIP2[5] / PC5 MSCIP2[4] / PC4 MSCIP2[3] / PC3 MSCIP2[2] / PC2 MSCIP2[1] / PC1 SPISCK / PE6 SPIMOSI / PE5 PE0 VDD33_3
VSS_1 VDD33_1 PE1 PB6 / MSCIP1[14] PB7 / MSCIP1[15] PA0 / MSCIP1[0] PA1 / MSCIP1[1] PA2 / MSCIP1[2] PA3 / MSCIP1[3] PA4 / MSCIP1[4] VSS_5 VDD33_5 PA5 / MSCIP1[5] PA6 / MSCIP1[6] PA7 / MSCIP1[7] PD0 / MSCIP2[8]
PD1 / TOCP2 / MSCIP2[9] PD2 / TICP2 / MSCIP2[10] PD3 / TEXTCLK / MSCIP2[11] VSS_2 VDD33_2 PD4 / MSCIP2[12] PE7 / SPIMISO RESET PD5 / MSCIP2[13] PD6 / MSCIP2[14] PD7 / MSCIP2[15] PE2 / ICC_DATA PE3 / ICC_CLK PE4 / SPI SS PC0 / MSCIP2[0] VSS_3
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PIN DESCRIPTION (Cont'd) Legend / Abbreviations for tables 2 thru 6: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level:r CT = CMOS 0.3VDD/0.7VDD with input trigger TT= TTL 0.8V / 2V with Schmitt trigger Output level: D8 = 8mA drive D4 = 4mA drive D2 = 2mA drive Port and control configuration: - Input:float = floating, wpu = weak pull-up, wpd = weak pull-down, int = interrupt - Output: OD = pseudo open drain, PP = push-pull Table 1. Power Supply
Pin TQFP48 TQFP64 Type Pin Name Description
48 47 33 32 25 24 14 15
64 VSS_1 63 VDD33_1 45 VSS_2 44 VDD33_2 33 VSS_3 32 VDD33_3 18 VSS_4 19 VDD33_4 54 VSS_5 53 VDD33_5
S S S S S S S S S S S
Ground I/Os and Regulator supply voltage Ground I/Os and Regulator supply voltage Ground I/Os and Regulator supply voltage Ground I/Os and Regulator supply voltage Ground I/Os supply voltage USB PHY, OSC and PLL power supply output (1.8V)
13
17 VDDOUSB
Table 2. Control & System
Pin TQFP48 TQFP64 Pin Name Power Type Description
29
41 RESET
I
3.3 Reset input with filter and pull-up
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PIN DESCRIPTION (Cont'd) Table 3. USB 2.0 Interface
Pin TQFP48 TQFP64 Type Pin Name Description
12 11 10 9 8 7 6 5
16 VDDBL 15 VSSBL 14 USBDM 13 USBDP 12 VDD3 11 VDDC 10 VSSC 9 RREF
S S
Supply voltage for buffers and deserialisation ffs (1.8V) Ground for buffers and deserialisation ffs (1.8V)
I/O USB DATA I/O USB DATA + S S S A Supply voltage for the FS compliance (3.3V) Supply voltage for DLL & xor tree (1.8V) Ground for DLL & xor tree (1.8V) Ref. resistor for integrated impedances process adapt (11.5kohms 1% Pull Down)
Table 4. USB 2.0 and core Clock System
Pin TQFP48 TFQP64 Type Pin Name Description
4 3 2 1
8 7 6 5
VSSA OSCOUT OSCIN VDDA
S O I S
Ground for osc & PLL (1.8V) 12MHz oscillator output 12MHz oscillator input Supply voltage for osc & PLL (1.8V)
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PIN DESCRIPTION (Cont'd) Table 5. General Purpose I/O Ports / Mass Storage I/Os
5V tolerant Pin Type TQFP48 TQFP64 Pin Name Level Outputs Input Configuration Input float wpu int Main Output function (after reset) OD PP X X X ei0 X X X X X X X X ei1 X X X X X X X X ei2 X X X X X X X X ei3 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port A6 Port A7 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Port C0 Port C1 Port C2 Port C3 Port C4 Port C5 Port C6 Port C7 Port D0 Port D1 Port D2 Port D3 Port D4 Port D5 Port D6 Port D7 Timer OCP2 Timer ICP2 Timer OCP1 Timer ICP1 Alternate function
ALT1
ALT2 MSCIP1[0] MSCIP1[1] MSCIP1[2] MSCIP1[3] MSCIP1[4] MSCIP1[5] MSCIP1[6] MSCIP1[7] MSCIP1[8] MSCIP1[9] MSCIP1[10] MSCIP1[11] MSCIP1[12] MSCIP1[13] MSCIP1[14] MSCIP1[15] MSCIP2[0] MSCIP2[1] MSCIP2[2] MSCIP2[3] MSCIP2[4] MSCIP2[5] MSCIP2[6] MSCIP2[7] MSCIP2[8] MSCIP2[9] MSCIP2[10] MSCIP2[12] MSCIP2[13] MSCIP2[14] MSCIP2[15]
45 44 43 42 41 40 39 38
59 PA0 58 PA1 57 PA2 56 PA3 55 PA4 52 PA5 51 PA6 50 PA7 21 PB0 (2) 20 PB1 4 3 2 1 PB3 PB5
(2)
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
(2)
TT D4 TT D4 TT D4 TT D4 TT D4 TT D4 TT D4 TT D4 TT D4 TT D4 TT D4 TT D4 TT D4 TT D4 TT D4 TT D4 TT D8 TT D8 TT D8 TT D8 TT D4 TT D4 TT D4 TT D4 TT D2 TT D2 TT D2 TT D2 TT D2 TT D2 TT D2 TT D2
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
PB2 (2)
(2)
PB4 (2)
(2)
61 PB6 (2) 60 PB7 (2) 26 22 21 20 19 18 17 16 37 36 35 34 31 34 PC0 28 PC1 27 PC2 26 PC3 25 PC4 24 PC5 23 PC6 22 PC7 49 PD0 48 PD1 47 PD2 46 PD3 43 PD4 40 PD5 39 PD6 (2) 38 PD7 (2)
Timer EXTCLK MSCIP2[11]
I/O I/O I/O
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5V tolerant
Pin Type TQFP48 TQFP64 Pin Name
Level Outputs Input
Configuration Input float wpu int
OD
PP
Main function Output (after reset) X X X X X X X X X X X X X X X X Port E0 Port E1 Port E2 Port E3 Port E4 Port E5 Port E6 Port E7
Alternate function
ALT1
ALT2
23 46 28 27
31 PE0 62 PE1 37 PE2 36 PE3
(1)
I/O I/O I/O I/O I/O I/O I/O X I/O X
TT D8 TT D8 TT D8 TT D8 TT D2 TT D2 TT D2 TT D2
X X X X X X X X
X X X X X X X X ei4
ICC_DATA ICC_CLK SPI SS SPI MOSI SPI SCK SPI MISO
35 PE4 (2) 30 PE5 (2) 29 PE6 (2) 30 42 PE7
Notes: 1. Caution: during normal operation this pin must be pulled-up, internally or externally. This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in pull-up 2. Ports unavailable in the 48-pin packages (PB7:0, PD7:5, PE6:4) are forced to input mode with internal pull-up activated to avoid possible floating I/O consumption.
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PIN DESCRIPTION (Cont'd) Figure 4. NAND Flash Drive Application Example (TQFP64: parallel access through up to 4 CEs)
ST7267
MSCI
8 8 6
PA PC PB PD
2
8
I/O
5
CTRL
2
8
I/O
5
CTRL
2
8
I/O
5
CTRL
2
8
I/O
5
CTRL
2
0~7
0~7
8-15
8-15
3.3V
8-bit NAND 1
8-bit NAND 2
8-bit NAND 3
UP TO 4 8-bit NAND 4
VDD
VDD
VDD
VDD
Table 6. NAND Interface Pin Assignment for different applications
NAND 16-bit parallel acIO[0-7] IO[8-15] cess through 4 CEs (1) ST7267 pins PA0-7 PB0-7 ALE PC0 CLE PC1 WE PC2 RE PC3 CE1 PC4 CE2 PC5
(2)
CE3 PC6
(2)
CE4 PC7
(2)
RnB PD0
WP PD1
Notes: 1. when 8-bit NANDs are connected, the TQFP48 package can be used 2. if only one NAND is used, these I/Os are free for other applications
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PIN DESCRIPTION (Cont'd) Figure 5. NAND Flash Drive Application Example (TQFP64: 16-bit parallel access on 8-bit NAND)
ST7267
MSCI
8 8 6
PA PC PB PD
2
8
I/O
5
2
8
I/O
5
CTRL
2
8
I/O
5
CTRL
2
8
I/O
5
CTRL
2
CTRL
0~7
0~7
8-15
8-15
3.3V
8-bit NAND 1
8-bit NAND 2
8-bit NAND 3
UP TO 4 8-bit NAND 4
VDD
VDD
VDD
VDD
Table 7. NAND Interface Pin Assignment (2 or 4 8-bit NANDs)
NAND Pin ST7267 pin
I/O0-7 PA0-7 ALE PC0 CLE PC1 WE PC2 RE PC3 CE1 PC4 I/O8-15 PB0-7 CE2 PC5(1) RnB PD0 WP PD1
Note: 1. When two NANDs have to be handled, this I/O is free for other functions. Pins from different chips should be tied together (i.e. CLE1 with CLE2...).
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3 ST7 REGISTER & MEMORY MAP
As shown in Figure 6, the ST7 core is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of: 80 bytes of register locations 4 Kbytes of ST7 DATA RAM (including up to 256 bytes for the stack from 0100h to 01FFh). 54 Kbytes of ST7 CODE ROM program memory The highest address bytes contain the user reset and interrupt vectors in ROM which are remapped in ST7 DATA RAM. Two memory spaces are addressable by both the ST7 and the MSCI 2 Kbytes of MSCI CODE RAM 5 Kbytes of dual-ported RAM 3.1 PAGED MEMORY SPACE The MSCI CODE RAM and the DPRAM are mapped in the same address range on the ST7 bus (1100h to 24FFh). During initialisation, the MSCI program code has to be loaded in the MSCI CODE RAM by the ST7 To do this, set the RAMLD bit in the MSCI Control Register (MCR). This can only be done while the MSCI is reset state. Refer to section 14.2.3 on page 116 for details. When the MSCI code is loaded, clear the RAMLD bit to disable any further access to MSCI CODE RAM from the ST7 bus. For a description of the MSCI Register and Memory Map, refer to section 12 on page 111. 3.2 INTERRUPT AND VECTOR REMAPPING For flexibility, the interrupt and reset vectors can be mapped in RAM. See section 7.5 on page 39. IMPORTANT: Memory locations noted "Reserved" must never be accessed. Accessing a reserved area generates a hardware reset of the device.
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Figure 6. ST7 Memory Map
0000h 007Fh 0080h
Hardware Registers (see Table 6) ST7 DATA RAM (4224 Bytes)
0080h 00FFh 0100h 01FFh 0200h
Short Addressing memory (128 Bytes) Stack (256 Bytes) 16-bit Addressing memory (3840 Bytes)
10DFh 10E0h 10FFh
Interrupt & Reset Vectors (1)
10FFh
1100h
1100h
MSCI CODE RAM (2 KBytes)
18FFh 1900h
RAMLD reset
RAMLD set
DPRAM (5 KBytes)
Reserved (3 KBytes)
24FFh
24FFh
2500h 27FFh 2800h
Reserved (768 Bytes)
ST7 CODE ROM (54K Bytes)
FFDFh FFE0h
Interrupt & Reset Vectors (1) (see Table 9) FFFFh
(1) vectors remapped in RAM see section 7.5 on page 39
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Table 8. Hardware Register Memory Map
@ 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah to 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh ST7 I/O Ports EP2DR PADR PADDR PAOR PBDR PBDDR PBOR Endpoint 2 Data Register Port A Data Register Port A Data Direction Register Port A Option Register Port B Data Register Port B Data Direction Register Port B Option Register xxh 00h(1) 00h 00h 00h(1) 00h 00h r/w r/w r/w r/w r/w r/w r/w USBHS EP0DR EP1DR Endpoint 0 Data Register Endpoint 1 Data Register xxh xxh r/w r/w Reserved (6 Bytes) USBHS ITOUTER ITUSBER ITUSBR FRNBRM FRNBRL TSTMODE INDEXR INMAXPRM INMAXPRL INCSRM INCSRL OUTMAXPRM OUTMAXPRL OUTCSRM OUTCSRL OUTCNTRM OUTCNTRL ITINER ITOUTR ITINR Block Register Label PWRR FADDR Register name PoWeR management Register Function ADDress Register Not used. Always return 00h Interrupt EP0 and IN EP Register Not used. Always return 00h Interrupt OUT EP Register Not used. Always return 00h Interrupt IN Enable Register Not used. Always return 00h Interrupt OUT Enable Register Interrupt USB Enable Register Interrupt USB Register FRame NumBer Register (MSB) FRame NumBer Register (LSB) TeST MODEs INDEX Register IN EP n Max Pkt size Register (MSB) IN EP n Max Pkt size Register (LSB) IN EP n Control Status Register (MSB) Control Status Reg for EP0 or IN EP n (LSB) OUT EP n Max Pkt size Register (MSB) OUT EP n Max Pkt size Register (LSB) OUT EP n Control Status Register (MSB) OUT EP n Control Status Register (LSB) OUT EP n Count Register (MSB) OUT EP n Count Register (LSB) 06h 06h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h r/w r/w r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r 07h r/w 00h r 00h r Reset Status 20h 00h Remarks r/w r/w
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@ 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h
Block
Register Label PCDR PCDDR PCOR PDDR PDDDR PDOR PEDR PEDDR PEOR WDGCR ISPR0 ISPR1 ISPR2 ISPR3 EICR0 EICR1 PAEIENR PBEIENR PCEIENR PDEIENR PEEIENR PAEISR PBEISR PCEISR PDEISR PEEISR TCR2 TCR1 TCSR TIC1HR TIC1LR TOC1HR TOC1LR
Register name Port C Data Register Port C Data Direction Register Port C Option Register Port D Data Register Port D Data Direction Register Port D Option Register Port E Data Register Port E Data Direction Register Port E Option Register Watchdog Control Register Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 External Interrupt Control Register 0 External Interrupt Control Register 1 Port A External Interrupt Enable register Port B External Interrupt Enable register Port C External Interrupt Enable register Port D External Interrupt Enable register Port E External Interrupt Enable register Port A External Interrupt Status Register Port B External Interrupt Status Register Port C External Interrupt Status Register Port D External Interrupt Status Register Port E External Interrupt Status Register Timer Control Register 2 Timer Control Register 1 Timer Control/Status Register Timer Input Capture 1 High Register Timer Input Capture 1 Low Register Timer Output Compare 1 High Register Timer Output Compare 1 Low Register Timer Counter High Register Timer Counter Low Register Timer Alternate Counter High Register Timer Alternate Counter Low Register Timer Input Capture 2 High Register Timer Input Capture 2 Low Register Timer Output Compare 2 High Register Timer Output Compare 2 Low Register Miscellaneous Register 1
Reset Status 00h(1) 00h 00h 00h
(1)
Remarks r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r/w r/w r r r r r r r/w r/w r/w
ST7 I/O Ports
00h 00h 00h(1) 00h 00h 7Fh FFh FFh FFh FFh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h 00h
WDG
ITC
TIMER
TCHR TCLR TACHR TACLR TIC2HR TIC2LR TOC2HR TOC2LR
MISC
MISCR1
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@ 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h to 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h to 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch
Block
Register Label
Register name Reserved (1 Byte)
Reset Status
Remarks
TBU
TBUCVR TBUCSR
TBU Counter Value Register TBU Control/Status Register Reserved (1 Byte)
00h 00h
r/w r/w
CCMR CKGEN CELSPCR CEHSPCR EOSSR EOSCR SPIDR SPI SPICR SPICSR
CKGEN Control Mode Register CKGEN Enable of Low Speed Periph. CLK Reg. CKGEN Enable of High Speed Periph. CLK Reg. End Of Suspend Status Register End Of Suspend Control Register SPI Data I/O register SPI Control Register SPI Control/Status Register
00h 00h 00h 00h 00h xxh 0xh 00h
r/w r/w r/w r/w r/w r/w r/w r
EOS
Reserved (5 Bytes)
MCR MSR MPCM MSCI MPCL MCRCH MCRCL
MSCI Control Register MSCI Status Register MSCI PC register (MSB) MSCI PC register (LSB) MSCI CRC (MSB) MSCI CRC (LSB)
01h 00h 00h 00h 00h 00h
r/w r/w r/w r/w r r
Reserved (4 Bytes) DMCR DMCSR DMBK1M DMBK1L DM(2) DMBK2M DMBK2L DMCR2 DMCSR2 DMENFCT Debug Module Control Register Debug Module Control / Status Register Debug Module BreaKpoint 1 register (MSB) Debug Module BreaKpoint 1 register (LSB) Debug Module BreaKpoint 2 register (MSB) Debug Module BreaKpoint 2 register (LSB) Debug Module Control Register 2 Debug Module Control / Status Register 2 Debug Module Enable Function register 00h 10h FFh FFh FFh FFh 00h 00h FFh r/w r/w r/w r/w r/w r/w r/w r r/w
Legend: x=undefined, r/w=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. For a description of the registers of the Debug Module used for In-Circuit Debugging, see ICC reference manual.
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Table 9. Interrupt Mapping
N Source Block RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 USB EOS MSCI EI0 EI1 EI2 EI3 EI4 SPI TIMER TBU Description Reset vector Software Interrupt vector NMI Interrupt USB Interrupt USB End of Suspend Interrupt MSCI interrupt External Interrupt Port A External Interrupt Port B External Interrupt Port C External Interrupt Port D External Interrupt Port E SPI interrupt Timer interrupt TimeBase Unit Register Label Priority Order Highest Priority Exit from HALT yes no no yes no yes yes yes yes yes yes no no Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h
N/A see Note 1 MSCI N/A N/A N/A N/A N/A SPICSR T1SR TBUCSR
Lowest Priority
Note 1: please see USB chapter
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4 ST7 CENTRAL PROCESSING UNIT
4.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 4.2 MAIN FEATURES

Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
4.3 CPU REGISTERS The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. Figure 7. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0
Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value
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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z
Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1
0 C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.
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CENTRAL PROCESSING UNIT (Cont'd) STACK POINTER (SP) Read/Write Reset Value: 01FFh
15 0 7 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 0 0 0 0 0 8 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following a CPU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. Figure 8. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event PUSH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
POP Y
IRET
RET or RSP
SP SP CC A X PCH SP PCH @ 01FFh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 01FFh Stack Lower Address = 0100h
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5 ST7 POWER SAVING MODES
5.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, three main power saving modes are implemented in the Device (see Figure 9): Low Power Mode (PLL OFF) Wait Halt After a RESET low power mode is selected by default. This mode drives the Device (CPU and embedded peripherals except USB) by means of a master clock which is based on the main oscillator frequency. From this low power mode, different modes may be selected using specific CPU instruction. Important note: Moreover, if the USB cell is not used, the UPO bit of the EOSCR register must be set to avoid any USB2 PHY consumption. Figure 9. Power Saving Mode Transitions
High FPRUN FPWAIT LPRUN LPWAIT HALT
Figure 10. WAIT Mode Flow Chart
WFI INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I1, I0 BITS
ON ON OFF CLEARED
N RESET N INTERRUPT
Y
Y
OSCILLATOR PERIPH. CLOCK CPU CLOCK I1, I0 BITS1)
ON ON ON
Low POWER CONSUMPTION
IF RESET 512 CPU CLOCK CYCLES DELAY
5.2 WAIT MODE WAIT mode places the Device in a low power consumption mode by stopping the CPU. This power saving mode is selected by executing the "WFI" CPU instruction. All peripherals remain active. During WAIT mode, the I bits in the CC register are forced to 0, enabling all interrupts. All other registers and memory remain unchanged. The Device remains in WAIT mode until an interrupt or reset occurs. If the event is an interrupt, the program counter immediately branches to the starting address of the interrupt or reset service routine. If the wake up event is a reset, before fetching the reset vector, there is a 512 CPU clock cycle delay to allow for stabilization. Refer to Figure 10.
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: 1) Before servicing an interrupt, the CC register is pushed on the stack. The I0 and I1 bit values for each interrupt are predefined by the user in the ISPRx register. During the interrupt routine these values are loaded into I0 and I1 bits and cleared when the CC register is popped.
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ST7 POWER SAVING MODES (Cont'd) 5.3 HALT MODE HALT mode is the lowest power consumption mode. HALT mode is entered by executing the HALT instruction. The internal oscillator is stopped, causing all internal processing to be stopped, including the operation of the on-chip peripherals. To further decrease the consumption (especially for the Suspend mode): - The internal regulator must be put in powerdown mode by setting the REG_OFF bit of the CCMR register. - The active slew rate compensation cell of the IOs must be stopped by setting the CPO bit of the EOSCR register. Entering HALT mode clears the I bits in the CC register, enabling interrupts. If an interrupt is pending, the Device wakes up immediately. Not all interrupts will wake up the Device from HALT, only those listed in the Interrupt Mapping Table in the Interrupt section allow wake-up. Specific interrupts such as an external interrupt or an USB end of suspend interrupt (as described in Table 16) or a reset wakes up the Device from HALT mode. - If a reset is the wake-up event, the main oscillator is immediately turned on and a 512 CPU cycle delay is used to stabilize the oscillator. After the start up delay the device starts in Low power mode and the CPU resumes operation by fetching the reset vector. - If an interrupt is the wake-up event, the main oscillator is immediately turned on and a 512 CPU cycle delay is used to stabilize the oscillator. After the start up delay, if the device was in low power mode before entering in halt mode the device starts in low power mode and the CPU resumes operation. But if the device was in full power mode before entering in halt, the operation are resumed only after the PLL lock Refer to Figure 11 for more details. 5.3.1 HALT MODE RECOMMENDATIONS - Make sure that an external event is available or that the USB end of suspend interrupt is enabled to wake up the Device from Halt mode. - When using an external interrupt to wake up the Device, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. - For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. - The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. - As the HALT instruction clears the I bits in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).
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ST7 POWER SAVING MODES (Cont'd) Figure 11. HALT Mode Flow Chart
HALT INSTRUCTION
MODE: OSCILLATOR PERIPH. CLOCK PLL CPU CLOCK N RESET N
INTERRUPT
OFF OFF OFF OFF
Y
Y RESET WAKEUP MODE: INT. WAKEUP MODE: OSCILLATOR PERIPH. CLOCK CPU CLOCK ON OFF OFF OSCILLATOR PERIPH. CLOCK CPU CLOCK Note: No software execution while oscillator stabilizes. ON OFF OFF
512 CLOCK CYCLES DELAY N Y LOW POWER MODE BEF. HALT N PLL startup delay LOW POWER MODE: OSCILLATOR PERIPH. CLOCK PLL CPU CLOCK ON OFF OFF ON 512 CLOCK CYCLES DELAY
LOW POWER MODE: OSCILLATOR ON PERIPH. CLOCK (1) PLL OFF CPU CLOCK ON
FETCH RESET VECTOR FULL POWER MODE: OSCILLATOR ON PERIPH. CLOCK (1) ON PLL CPU CLOCK ON
SERVICE INTERRUPT
1)
periph. clock status is the one before the halt according to CER register.
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6 ST7 I/O PORTS
6.1 INTRODUCTION The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for onchip peripherals or analog input. 6.2 FUNCTIONAL DESCRIPTION A Data Register (DR) and a Data Direction Register (DDR) are always associated with each port. The Option Register (OR), which allows input/output options, may or may not be implemented. The following description takes into account the OR register. Refer to the Port Configuration table for Device specific information. An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit x corresponding to pin x of the port. Figure 12 shows the generic I/O block diagram. 6.2.1 Input Modes Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital value from that I/O pin. If an OR bit is available, different input modes can be configured by software: floating or pull-up. Refer to I/O Port Implementation section for configuration. Note: Writing to the DR modifies the latch value but does not change the state of the input pin. External Interrupt Function In input mode, external interrupts can be enabled by setting the corresponding bit in the PxEIENR register. Falling or rising edge sensitivity is programmed independently for each interrupt vector. The External Interrupt Control Register (EICR) controls this sensitivity. Several pins may be tied to one external interrupt vector. Refer to Pin Description to see which ports have external interrupts. External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Modifying the sensitivity bits will clear any pending interrupts. 6.2.2 Output Modes Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the I/O through the latch. Reading the DR bits returns the previously stored value. If an OR bit is available, different output modes can be selected by software: push-pull or opendrain. Refer to I/O Port Implementation section for configuration. Table 10. DR value and output pin status
DR 0 1 Push-Pull VOL VOH Open-Drain VOL Floating
Note: When switching from input to output mode, first set the DR bit to set the correct level to be applied on the pin, then write the DDR to configure the pin as an output. 6.2.3 Alternate Functions Many I/Os of the Device have one or more alternate functions to output. This may include output signals from, or input signals to, on-chip peripherals. The Device Pin Description table describes which peripheral signals can be input/output to which ports. A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripheral's control register). The peripheral configures the I/O as an output and takes priority over standard I/ O programming. The I/O's state is readable by addressing the corresponding I/O data register. Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this will increase current consumption. Before using an I/O as an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur. Configure an I/O as input floating for an on-chip peripheral signal which can be input and output. Caution: I/Os which can be configured as both an analog and digital alternate function need special attention. The user must control the peripherals so that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function.
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ST7 I/O PORTS (Cont'd) Figure 12. I/O Port General Block Diagram (1)
REGISTER ACCESS ALTERNATE OUTPUT
From on-chip peripheral (2)
1 0
V33DD
P-BUFFER (see table below) PULL-UP (see table below)
ALTERNATE ENABLE BIT DR
VDD33
DDR
PULL-UP CONDITION
DATA BUS
PAD
OR OR SEL N-BUFFER DDR SEL DIODES (see table below)
PxEIENR
DR SEL
1 0
SCHMITT TRIGGER
ALTERNATE INPUT
Combinational Logic To on-chip peripheral (2)
EXTERNAL INTERRUPT REQUEST (eix)
SENSITIVITY SELECTION
FROM OTHER BITS
Notes: 1. Refer to the Port Configuration table for Device specific information. 2. MSCI can control Port A, B, C and D. See the MSCI I/0 Ports chapter. Table 11. ST7 I/O Port Mode Options
Diodes Configuration Mode Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer to V33 OR VDD VDD On to VSS
Input
Off On Off NI On
Output
NI (see note)
Legend:
NI - not implemented Off - implemented not activated On - mplemented and activated
Note: The diode to V33 OR VDD VDD is not implemented in the true open drain pads. A local protection between the pad and VOL is implemented to protect the device against possible stress.
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ST7 I/O PORTS (Cont'd) Figure 13. Standard I/O Port Configurations
Hardware Configuration
VDD33
VDD33
RPU PULL-UP CONDITION
DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1)
PAD
ALTERNATE INPUT to on-chip peripherals EXTERNAL INTERRUPT SOURCE (eix) INTERRUPT CONDITION
OPEN-DRAIN OUTPUT 2)
VDD33
VDD33
RPU
VDD33
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
VDD33 PUSH-PULL OUTPUT 2)
VDD33
RPU
VDD33
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE BIT
ALTERNATE OUTPUT from on-chip peripherals
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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ST7 I/O PORTS (Cont'd) 6.3 ST7 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific I/O port features such as ADC input or open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. 6.4 UNUSED I/O PINS Unused I/O pins must be connected to fixed voltage levels. Refer to the Electrical Characteristics Section. 6.5 LOW POWER MODES
Mode WAIT HALT Description No effect on I/O ports. External interrupts cause the Device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the Device to exit from HALT mode.
6.6 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and PxEIENR registers and if the I bit in the CC register is cleared (RIM instruction).
Interrupt Event External interrupt on selected external event Event Flag Enable Control Bit DDRx PxEIENR Exit from Wait Yes Exit from Halt Yes
-
Table 12. ST7 I/O Port Configuration
Port 1) Port A Port B Port C Port D Port E Pin name PA7:0 PB7:0 PC7:0 PD7:0 PE7:0 Input OR = 0 floating floating floating floating floating OR = 1 pull-up pull-up pull-up pull-up pull-up OR = 0 open drain open drain open drain open drain open drain Output OR = 1 push-pull push-pull push-pull push-pull push-pull
Note: 1) Ports unavailable in the 48-pin packages (PB7:0, PD7:5, PE6:4) are forced to input mode with internal pull-up activated to avoid possible floating I/O consumption.
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ST7 I/O PORTS (Cont'd) 6.7 REGISTER DESCRIPTION DATA REGISTER (DR) Port x Data Register PxDR with x = A, B, C, D or E. Read/Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode OPTION REGISTER (OR) Port x Option Register PxOR with x = A,B, C, D, or E. Read/Write Reset Value: 0000 0000 (00h)
7 O7 O6 O5 O4 O3 O2 O1 0 O0
Bits 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register always returns the digital value applied to the I/O pin (pin configured as input). Note: For this register, bits corresponding to I/O ports which are unavailable in the 48-pin package are read as 1. DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B, C, D or E. Read/Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0
Bits 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the interrupt capability or the basic configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: Floating input 1: Floating input with interrupt. Output mode: 0: Output open drain (with P-Buffer deactivated) 1: Output push-pull
Bits 7:0 = DD[7:0] Data direction register 8 bits.
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ST7 I/O PORTS (Cont'd) Table 13. ST7 I/O Port Register Map and Reset Values
Address (Hex.) Register Label 1) 2) 7 0 MSB 6 0 5 0 4 0 3 0 2 0 1 0 0 0 LSB
Reset Value of all I/O port registers 0026h PADR 0027h PADDR 0028h PAOR 0029h PBDR 002Ah PBDDR 002Bh PBOR 002Ch PCDR 002Dh PCDDR 002Eh PCOR 002Fh PDDR 0030h PDDDR 0031h PDOR 0032h PEDR 0033h PEDDR 0034h PEOR
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Notes: 1. PxDDR and PxOR bits corresponding to IOs which are unavailable in the 48-pin package are forced to 0. They are write protected. 2. PxDR bits corresponding to IOs which are unavailable in the 48-pin package are read as 1.
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7 ST7 INTERRUPTS
7.1 INTRODUCTION The ST7 enhanced interrupt management provides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: - Up to 4 software programmable nesting levels - Up to 16 interrupt vectors fixed by hardware - 2 non maskable events: RESET, TRAP This interrupt management is based on: - Bit 5 and bit 3 of the CPU CC register (I1:0), - Interrupt software priority registers (ISPRx), - Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller. 7.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 14). The processing flow is shown in Figure 14 Figure 14. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y TRAP? Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y
When an interrupt request has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 14. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1
High
FETCH NEXT INSTRUCTION
THE INTERRUPT STAYS PENDING
Y
IRET? N
RESTORE PC, X, A, CC FROM STACK
EXECUTE INSTRUCTION
STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR
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ST7 INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: - the highest software priority interrupt is serviced, - if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 15 describes this decision process. Figure 15. Priority Decision Process
PENDING INTERRUPTS
I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode. TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 14.
RESET The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.
Same
SOFTWARE PRIORITY
Different
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET and TRAP are non maskable and they can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 14). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and
Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed. Peripheral Interrupts Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.
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ST7 INTERRUPTS (Cont'd) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit from WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from HALT mode (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 15. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. Figure 16. Concurrent Interrupt Management
TRAP SOFTWARE PRIORITY LEVEL IT0 IT2 IT1 IT4 IT3 I1 I0
7.4 CONCURRENT & NESTED MANAGEMENT The following Figure 16 and Figure 17 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 17. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure.
HARDWARE PRIORITY
TRAP IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1
3 3 3 3 3 3 3/0 10
11 11 11 11 11 11
11 / 10 Figure 17. Nested Interrupt Management
TRAP
SOFTWARE PRIORITY LEVEL
IT2
IT1
IT4
IT3
IT0
I1
I0
HARDWARE PRIORITY
TRAP IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2
3 3 2 1 3 3 3/0 10
11 11 00 01 11 11
11 / 10
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USED STACK = 20 BYTES
USED STACK = 10 BYTES
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ST7 INTERRUPTS (Cont'd) Table 15. Dedicated Interrupt Instruction Set
Instruction HALT IRET JRM JRNM POP CC RIM SIM TRAP WFI New Description Entering Halt mode Interrupt routine return Jump if I1:0=11 Jump if I1:0<>11 Pop CC from the Stack Enable interrupt (level 0 set) Disable interrupt (level 3 set) Software trap Wait for interrupt Pop CC, A, X, PC I1:0=11 ? I1:0<>11 ? Mem => CC Load 10 in I1:0 of CC Load 11 in I1:0 of CC Software NMI I1 1 1 1 1 H I0 0 1 1 0 N Z C Function/Example I1 1 I1 H H I0 0 I0 N Z C N Z C
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions. In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never be used in an interrupt routine.
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ST7 INTERRUPTS (Cont'd) 7.5 INTERRUPT VECTOR TABLE MANAGEMENT For added flexibility, the ST7267 features two interrupt vector table modes. After reset, the interrupt vectors are located in ROM. The application can switch the vectors to RAM by executing the procedure given below. Prior to switching the vectors to RAM, the RAM area must be initialised. Table 16. Interrupt Mapping
N Source Block RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 USB EOS MSCI EI0 EI1 EI2 EI3 EI4 SPI TIMER TBU Description Reset vector Software Interrupt vector Unused USB Interrupt USB End of Suspend Interrupt MSCI interrupt External Interrupt Port A External Interrupt Port B External Interrupt Port C External Interrupt Port D External Interrupt Port E SPI interrupt Timer interrupt TimeBase Unit Register Label Priority Order Highest Priority Exit from HALT yes no no yes no yes yes yes yes yes yes no no Address Vector (2) FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h
To switch the vectors from ROM to RAM: 1. Initialise the RAM area with the correct interrupt vectors 2. Set the USVR bit in the MISC1 register to enable the interrupt vector table in RAM
N/A
(1)
EOSSR MSCI N/A N/A N/A N/A N/A SPICSR T1SR TBUCSR
Lowest Priority
Notes: 1. see USB chapter section 10.5 on page 93 2. This is the vector address in ROM. If the vector table is in RAM the address will be in the range 10FFh to 10E4h.
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ST7 INTERRUPTS (Cont'd) 7.6 EXTERNAL INTERRUPTS When an event occurs on an I/O port, this incoming signal is interpreted as an external interrupt. This signal can also be used to wake up the Device from HALT. There are several controlling factors for external interrupts: - Priority (Hardware and Software) - Enable/Disable control bits - Sensitivity Control - Status Flag Up to 8 signals on 8 ports can share one external interrupt. For example, ei0 is shared on all 8 ports of Port A. 7.6.1 Software and Hardware Priorities External interrupts have default priorities associated with them. They are as listed in the Interrupt Mapping table. These are the hardware priorities and are unchangeable. Software priorities are user assigned by programming the appropriate bits in the Interrupt Software Priority register (ISPRx) for a given external interrupt. The whole external interrupt group will have the same priority. For example, ISPR1 bits[0:1] control the software priority for Port A's external interrupt, ei0. These two types of priorities are important to manage because they function in the same manner as other interrupts for concurrent and nested modes. 7.6.2 Enable and Sensitivity Controls At an external interrupt event, for the interrupt to be acknowledged, it must be enabled. There is a control bit for each external interrupt. They are found in the External Interrupt Enable Port x register (PxEINENR). The external interrupt sensitivity is controlled by the ISxx bits in the EICRx registers (Figure 18). This control allows to have up to 4 fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four different events on the pin: Falling edge Rising edge Falling and rising edge Falling edge and low level To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). 7.6.3 Status Flag When an event occurs signalling that an external interrupt is requested, a flag is set by hardware. This flag informs the user which external interrupt has occurred. Each external interrupt has its own specific flag. They are found in the External Interrupt Port x register (PxEISR). If the corresponding external interrupt is enabled when this flag is set, the external interrupt is serviced. If several interrupts are pending, the interrupts are serviced according to their priority (software and or hardware, according to which interrupt mode is being employed). If there is an unwanted pending interrupt, it can be cleared by writing a different value in the ISx[1:0] in the EICRx registers.
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ST7 INTERRUPTS (Cont'd) Figure 18. Port x External Interrupt Control bits (x is A, B, C, D or E)
PORT x 7:0 INTERRUPTS EICRx PxOR.n PxDDR.n Pxn ISx1 ISx0
SENSITIVITY CONTROL PxEISR ITxF FLAG STATUS PxEIENR ITxE ENABLE CONTROL EXTERNAL INTERRUPT CONTROL BLOCK IT n IT n+7 ein INTERRUPT SOURCE
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ST7 INTERRUPTS (Cont'd) 7.7 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I0_9 I1_4 I1_8 I0_4 I0_8
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)
7 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 0 I0_0
Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1
ISPR2 ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1
I1_13 I0_13 I1_12 I0_12
High
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: TRAP and RESET events are non maskable sources and can interrupt a level 3 program.
These four registers contain the interrupt software priority of each interrupt vector. - Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondence is shown in the following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits
- Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. - Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).
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ST7 INTERRUPTS (Cont'd) EXTERNAL INTERRUPT CONTROL REGISTER 0 (EICR0) Read/Write Reset Value: 0000 0000 (00h)
7 0
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bits 1:0 = ISA[1:0] Port A ei0 sensitivity IT[7-0] The interrupt sensitivity, defined using the ISA[1:0] bits, is applied to the ei0 external interrupts:
ISA1 ISA0 0 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
ISD1 ISD0 ISC1 ISC0 ISB1 ISB0 ISA1 ISA0
Bit 7:6 =ISD[1:0] Port D ei3 sensitivity IT[31-24] The interrupt sensitivity, defined using the ISD[1:0] bits, is applied to the ei3 external interrupts:
ISD1 ISD0 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
0 1 1
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). EXTERNAL INTERRUPT CONTROL REGISTER 1 (EICR1) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 ISE1 ISE0
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bits 5:4 = ISC[1:0] Port C ei2 sensitivity IT[23-16] The interrupt sensitivity, defined using the ISC[1:0] bits, is applied to the ei2 external interrupts:
ISC1 ISC0 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
Bit 7:2 = Reserved, must be kept cleared. Bit 1:0 =ISE[1:0] Port E ei4 sensitivity IT[39-32] The interrupt sensitivity, defined using the ISE[1:0] bits, is applied to the ei4 external interrupts:
ISE1 ISE0 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bits 3:2 = ISB[1:0] Port B ei1 sensitivityIT[15-8] The interrupt sensitivity, defined using the ISB[1:0] bits, is applied to the ei1 external interrupts:
ISB1 ISB0 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). PORT A EXTERNAL INTERRUPT ENABLE REGISTER (PAEIENR) Read/Write Reset Value: 0000 0000 (00h)
7 IT7E IT6E IT5E IT4E IT3E IT2E IT1E 0 IT0E
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ST7 INTERRUPTS (Cont'd) Bits 7:0 = ITxE Port A interrupt enable These bits are set and cleared by software. 0: ITx external interrupt disabled. 1: ITx external interrupt enabled. PORT B EXTERNAL INTERRUPT ENABLE REGISTER (PBEIENR) Read/Write Reset Value: 0000 0000 (00h)
7 IT15E IT14E IT13E IT12E IT11E IT10E IT9E 0 IT8E
PORT E EXTERNAL INTERRUPT ENABLE REGISTER (PEEIENR) Read/Write Reset Value: 0000 0000 (00h)
7 0
IT39E IT38E IT37E IT36E IT35E IT34E IT33E IT32E
These bits are set and cleared by software. Bits 7:0 = ITxE Port E interrupt enable 0: ITx external interrupt disabled. 1: ITx external interrupt enabled.
Bits 7:0 = ITxE Port B interrupt enable These bits are set and cleared by software. 0: ITx external interrupt disabled. 1: ITx external interrupt enabled. PORT C EXTERNAL INTERRUPT ENABLE REGISTER (PCEIENR) Read/Write Reset Value: 0000 0000 (00h)
7 0
PORT A EXTERNAL INTERRUPT STATUS REGISTER (PAEISR) Read/Write Reset Value: 0000 0000 (00h)
7 IT7F IT6F IT5F IT4F IT3F IT2F IT1F 0 IT0F
IT23E IT22E IT21E IT20E IT19E IT18E IT17E IT16E
These bits are set and cleared by software. Bits 7:0 = ITxE Port C interrupt enable 0: ITx external interrupt disabled. 1: ITx external interrupt enabled. PORT D EXTERNAL INTERRUPT ENABLE REGISTER (PDEIENR) Read/Write Reset Value: 0000 0000 (00h)
7 0
Bits 7:0 = ITxF Port A interrupt flag These bits are set by hardware and cleared by software (by writing 0). 0: ITx external interrupt not requested. 1: ITx external interrupt requested. PORT B EXTERNAL INTERRUPT STATUS REGISTER (PBEISR) Read/Write Reset Value: 0000 0000 (00h)
7 IT15F IT14F IT13F IT12F IT11F IT10F IT9F 0 IT8F
IT31E IT30E IT29E IT28E IT27E IT26E IT25E IT24E
These bits are set and cleared by software. Bits 7:0 = ITxE Port D interrupt enable 0: ITx external interrupt disabled. 1: ITx external interrupt enabled.
Bits 7:0 = ITxF Port B interrupt flag These bits are set by hardware and cleared by software (by writing 0). 0: ITx external interrupt not requested. 1: ITx external interrupt requested.
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ST7 INTERRUPTS (Cont'd) PORT C EXTERNAL INTERRUPT STATUS REGISTER (PCEISR) Read/Write Reset Value: 0000 0000 (00h)
7 0
PORT D EXTERNAL INTERRUPT STATUS REGISTER (PDEISR) Read/Write Reset Value: 0000 0000 (00h)
7 0
IT23F IT22F IT21F IT20F IT19F IT18F IT17F IT16F
IT31F IT30F IT29F IT28F IT27F IT26F IT25F IT24F
Bits 7:0 = ITxF Port C interrupt flag These bits are set by hardware and cleared by software (by writing 0). 0: ITx external interrupt not requested. 1: ITx external interrupt requested.
Bits 7:0 = ITxF Port D interrupt flag These bits are set by hardware and cleared by software (by writing 0). 0: ITx external interrupt not requested. 1: ITx external interrupt requested. PORT E EXTERNAL INTERRUPT STATUS REGISTER (PEEISR) Read/Write Reset Value: 0000 0000 (00h)
7 0
IT39F IT38F IT37F IT36F IT35F IT34F IT33F IT32F
Bits 6:0 = ITxF Port E interrupt flag These bits are set by hardware and cleared by software (by writing 0). 0: ITx external interrupt not requested. 1: ITx external interrupt requested. DEBUG MODULE REGISTERS DM CONTROL REGISTER (DMCR) Read / Write Reset Value: 0000 0000 (00h)
7 0 MTR 0 0 0 0 0 0 0
Bit 7 = Reserved, must be kept cleared. Bit 6 = MTR Monitor Control. This bit must be set to access all DM registers, if this bit is cleared all DM registers except MTR bit are write protected. This bit is set by software or by hardware at the beginning of ICC Monitor execution. It is cleared by hardware at the end of the ICC Monitor.
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0: ICC Monitor program is not running 1: ICC Monitor program is running Bit 5:0 = Reserved, must be kept cleared. DM CONTROL REGISTER 2 (DMCR2) Read/Write Reset Value: 0000 0000 (00h) Bit 7:1= Reserved, must be kept cleared
7 0 0 0 0 0 0 0
0 SVR
Bit 0 = SVR Switch Interrupt Vectors to RAM This bit is set and cleared by software. It switches the interrupt vector table location to RAM 0: Interrupt vector table located in ROM 1: Interrupt vector table located in RAM
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ST7 INTERRUPTS (Cont'd) Table 17. Nested Interrupts Register Map and Reset Values
Address (Hex.) 0037h Register Label ISPR0 Reset Value ISPR1 Reset Value ISPR2 Reset Value ISPR3 Reset Value EICR0 Reset Value EICR1 Reset Value PAEIENR Reset Value PBEIENR Reset Value PCEIENR Reset Value PDEIENR Reset Value PEEIENR Reset Value PAEISR Reset Value PBEISR Reset Value PCEISR Reset Value PDEISR Reset Value PEEISR Reset Value DMCR Reset Value DMCR2 Reset Value 7 MSCI I1_3 1 EI3 0038h I1_7 1 TBU 0039h I1_11 1 I0_11 1 I0_7 1 I0_3 1 I1_2 1 EI2 I1_6 I0_6 1 1 TIMER I1_10 I0_10 1 1 I1_5 1 6 5 EOS I0_2 1 I1_1 1 EI1 I0_5 1 I1_4 1 4 3 USB 2 I0_1 1 1 EI0 I0_4 1 2 1 TLI 1 0
003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0074h 007Ah
1 ISD1 0 0 IT7E 0 IT15E 0 IT23E 0 IT31E 0 IT39E 0 IT7F 0 IT15F 0 IT23F 0 IT31F 0 IT39F 0 0 0
1 ISD0 0 0 IT6E 0 IT14E 0 IT22E 0 IT30E 0 IT38E 0 IT6F 0 IT14F 0 IT22F 0 IT30F 0 IT38F 0 MTR 0 0
1 ISC1 0 0 IT5E 0 IT13E0 0 IT21E 0 IT29E 0 IT37E 0 IT5F 0 IT13F 0 IT21F 0 IT29F 0 IT37F 0 0 0
1 ISC0 0 0 IT4E 0 IT12E 0 IT20E 0 IT28E 0 IT36E 0 IT4F 0 IT12F 0 IT20F 0 IT28F 0 IT36F 0 0 0
SPI I1_9 I0_9 1 1 Not used I1_13 I0_13 1 1 ISB1 ISB0 0 0 0 IT3E 0 IT11E 0 IT19E 0 IT27E 0 IT35E 0 IT3F 0 IT11F 0 IT19F 0 IT27F 0 IT35F 0 0 0 0 IT2E 0 IT10E 0 IT18E 0 IT26E 0 IT34E 0 IT2F 0 IT10F 0 IT18F 0 IT26F 0 IT34F 0 0 0
EI4 I1_8 I0_8 1 1 Not used I1_12 I0_12 1 1 ISA1 ISA0 0 0 ISE1 ISE0 0 0 IT1E IT0E 0 0 IT9E 0 IT17E 0 IT25E 0 IT33E 0 IT1F 0 IT9F 0 IT17F 0 IT25F 0 IT33F 0 0 0 IT8E 0 IT16E 0 IT24E 0 IT32E 0 IT0F 0 IT8F 0 IT16F 0 IT24F 0 IT32F 0 0 SVR 0
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8 ST7 CLOCK, RESET AND SUPPLY MANAGEMENT
8.1 CLOCK SYSTEM The main clock of the Device is generated by a 12 MHz crystal oscillator (main oscillator) The associated hardware configurations are shown in Table 18. Refer to the electrical characteristics section for more details. Crystal Oscillator The internal oscillator is designed to operate with a 12MHz AT-cut parallel resonant quartz. The crystal and associated components should be installed as close as possible to the input pins in order to minimize output distortion and start-up stabilization time. Figure 19. Clock Control Block Diagram Table 18. Device Clock Source
Hardware Configuration
Device
Crystal Oscillator
VDDA
OSCIN
OSCOUT
VDDA
CL1
LOAD CAPACITORS
CL2
FRQ bit 12MHz Crystal
delay counter
MODE bit clk_osc div 2, 4
fCPU Clock to CPU
0
clk_pll PLL
1
CCMR/CELSPCR /CEHSPCR CONTROL REG. Clock to Peripherals and MSCI
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8.2 CLOCK MANAGEMENT There are two types of run mode: Low power mode: the oscillator is the clock source (PLL is off). In this mode the USB clock domain is switched off (no 60 MHz clock is available). Full power mode for full operation with USB. The clock source is the PLL output (60 MHz). After reset the device starts running in low power mode. To switch to full power mode set MODE bit of CCMR. Control bits are also provided to enable or disable the clock to individual on-chip peripherals. In additional the application software can put the Device in Wait, HALT. 8.2.1 Register Description CLOCK CONTROL MODE REGISTER (CCMR) Read/Write Reset Value: 0000 0000 (00h)
7 REGOFF
(1)
Bit 7 = REGOFF Regulator mode in halt 0: Regulator ON 1: Regulator OFF Put the 3.3V to 1.8V regulator in power-down mode when the Halt instruction is executed. In this mode the 1.8V is provided but with low current sink capability (to maintain the RAM content and enable the wake-up). This bit has to be set before entering in halt mode. Note 1: This bit is automatically cleared after the wake-up from halt mode. Bit 6:3 = Reserved, must be kept cleared. Bit 2 = LOCK PLL lock (Read Only) This bit gives the PLL lock status. 0: PLL is not locked 1: PLL is locked Bit 1 = MODE Run mode This bit defines the device run mode. 0: Low power mode 1: Full power mode Bit 0 = FRQ CPU clock frequency This bit defines the CPU clock frequency. 0: Clock source frequency divided by 2. 1: Clock source frequency divided by 4.
0 0 0 0 0 LOCK MOD FRQ E
Table 19. Clock frequency selection
State
(1,2)
LOCK 0 0 0 0 1 1
MODE 0 0 1 1 1 1
FRQ 0 1 0 1 0 1
CPU clk 6 MHz 3 MHz 6 MHz 3 MHz 30 MHz 15 MHz
MSCI core clk 6 MHz 6 MHz 6 MHz 6 MHz 30 MHz 30 MHz
MSCI periph clk 12 MHz 12 MHz 12 MHz 12 MHz 60 MHz 60 MHz
USB clk No clk No clk No clk No clk 60 MHz 60 MHz
0 1 2 3 4 5
Notes: 1. state 2 and 3 are intermediate states waiting for PLL lock 2. state 4 cannot be used with the emulator.
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CLOCK MANAGEMENT (Cont'd) CLOCK ENABLE OF LOW SPEED PERIPHERALS CLK REGISTER (CELSPCR) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 0 TBU SPI WDG TIM 0 DM
0: SPI clock disabled 1: SPI clock enabled Bit 2 = WDG clock enable This bit enables the clock of the WDG. It is set and cleared by software. 0: WDG clock disabled 1: WDG clock enabled Note: when WDGHWR option is activated the watchdog clock is always enabled. Bit 1 = TIM Timer clock enable This bit enables the clock of the timer. It is set and cleared by software. 0: Timer clock disabled 1: Timer clock enabled Bit 0 = DM DM clock enable This bit enables the clock of the Debug Module. It is set by software and cannot be reset. 0: DM clock disabled 1: DM clock enabled
Bit 7:5 = Reserved, must be kept cleared. Bit 6 = TBU Timebase Unit This bit enables the clock of the Timebase Unit. It is set and cleared by software. 0: TBU clock disabled 1: TBU clock enabled Bit 3 = SPI SPI clock enable This bit enables the clock of the SPI. It is set and cleared by software.
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CLOCK MANAGEMENT (Cont'd) CLOCK ENABLE OF HIGH SPEED PERIPHERALS CLK REGISTER (CEHSPCR) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 USB DEC 0 ENC MSCI
Bit 2 = DEC Decoder clock enable This bit enables the clock of the Reed-Solomon decoder. It is set and cleared by software. 0: Decoder clock disabled 1: Decoder clock enabled Bit 1= ENC Encoder clock enable This bit enables the clock of the Reed-Solomon encoder. It is set and cleared by software. 0: Encoder clock disabled 1: Encoder clock enabled Bit 0 = MSCI MSCI clock enable This bit enables the clock of the MSCI. It is set and cleared by software. 0: MSCI clock disabled 1: MSCI clock enabled
Bit 7:4 = Reserved, must be kept cleared. Bit 3 = USB USB clock enable This bit enables the clock of the USB. It is set and cleared by software. 0: USB clock disabled 1: USB clock enabled
Table 20. Clock, Reset and Supply Control/Status Register Map and Reset Values
Address (Hex.) 005Bh 005Ch 005Dh Register Label CCMR Reset Value CELSPCR Reset Value CEHSPCR Reset Value 7 REGOFF 0 0 0 6 5 4 3 2 LOCK 0 WDG 0 DEC 0 1 MODE 0 TIM 0 ENC 0 0 FRQ 0 ICD 0 MSCI 0
0 0 0
0 0 0
0 TBU 0 0
0 SPI 0 USB 0
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8.3 RESET SEQUENCE MANAGER (RSM) 8.3.1 Introduction The reset sequence manager includes two RESET sources as shown in Figure 21: External RESET source pulse Internal WATCHDOG RESET Illegal Opcode reset The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the Device memory map. The basic RESET sequence consists of 3 phases as shown in Figure 20: Active Phase depending on the RESET source 512 CPU clock cycle delay RESET vector fetch The 512 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles. Figure 21. Reset Block Diagram Figure 20. RESET Sequence Phases
RESET
Active Phase INTERNAL RESET 512 CLOCK CYCLES FETCH VECTOR
8.3.2 Asynchronous External RESET pin The RESET pin is an input with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the Device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least tew(RSTL)in in order to be allow a correct internal start-up phase (see Figure 22). This detection is asynchronous and therefore the Device can enter reset state even in HALT mode.
VDD33
RON
RESET
Filter INTERNAL RESET
Pulse Generator
WATCHDOG RESET ILLEGAL OPCODE
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RESET SEQUENCE MANAGER (Cont'd) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 8.3.3 Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 22. Starting from the Watchdog counter underflow, the Device is reset internally for at least tiw(RSTL). Figure 22. RESET Sequences
8.3.4 Illegal Opcode reset In order to provide enhanced robustness to the device against unexpected behaviour, a system of illegal opcode detection is implemented. If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, combined with the Watchdog, allows the detection and recovery from an unexpected fault or interference. Note: A valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset.
EXTERNAL RESET
WDG ILLEG. OPCO. RESET
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
tew(RSTL)
tiw(RSTL)
EXTERNAL RESET SOURCE WATCHDOG RESET ILL. OPCODE WATCHDOG UNDERFLOW INTERNAL RESET INTERNAL RESET (512 TCPU) VECTOR FETCH
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8.4 SUPPLY MANAGEMENT The device operates with a single 3.3V supply power source. The 3.3V supply is converted to 1.8V by an internal voltage regulator. Figure 23. Supply Interconnections The VDDOUSB pad has to be connected to the VDDBL, VDDC and VDDA inputs of the chip through a filter.
VDD33
Filter Filter
2.2uF 220nF
1uF 10nF 10nF 10nF 10nF 10nF
220nF 100nF 100nF 100nF
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDDOUSB
VDDA
VDDC
VDDBL
Reg 3.3V to 1.8V
Internal supply
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9 ST7 MISCELLANEOUS REGISTER
MISCELLANEOUS REGISTER 1 (MISCR1) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 USVR 0 0 0 ST7V G
1: Interrupt vector table located in RAM Bits 2:1 = Reserved Bit 0= ST7VG ST7 VAC Guard This bit is set and cleared by software. It gives the priority to the ST7 for the access to USB registers or buffers (when an operation is on-going by the MSCI it will be finished) 0: USB access priority given to MSCI 1: USB access priority given to ST7
Bits 7:4 = Reserved Bit 3= USVR User Switch Interrupt Vector in RAM This bit is set and cleared by software. It switches the interrupt vector table location to RAM 0: Interrupt vector table located in ROM
Table 21. Miscellaneous Register Map and Reset Values
Address (Hex.) 0056h Register Label MISCR1 Reset Value 7 0 6 0 5 0 4 0 3 USVR 0 2 0 1 0 0 ST7VG 0
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10 ST7 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates a Device reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 10.1.2 Main Features Programmable free-running downcounter (64 increments of 131072 CPU cycles) Programmable reset Figure 24. Watchdog Block Diagram
Watchdog event (if the WDGA is set) when the T6 bit reaches zero Hardware Watchdog event selectable by option byte
10.1.3 Functional Description The counter value stored in the WDGCR register (bits T[6:0]), is decremented every 131072 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it generates a Watchdog reset.
RESET
WATCHDOG CONTROL REGISTER (WDGCR) WDGA T6 T5 T4 T3 T2 T1 T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER /135072
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WATCHDOG TIMER (Cont'd) The application program must write in the WDGCR register at regular intervals during normal operation to prevent a Watchdog reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the WDGCR register must be between FFh and C0h (see Table 22 .Watchdog Timing (fCPU = 15 MHz)): - The WDGA bit is set (watchdog reset enabled) - The T6 bit is set to prevent generating an immediate Watchdog reset - The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 22.Watchdog Timing (fCPU = 15 MHz) 10.1.4 Generating a Software reset The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 10.1.7 Low Power Modes
Mode WAIT
CR Register initial value Max Min FFh C0h
WDG timeout period (ms) 559.2 8.73
10.1.5 Software Watchdog Option If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 10.1.6 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used.
HALT
Description No effect on Watchdog: the downcounter continues to decrement. No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset. If an external interrupt is received, the Watchdog restarts counting after 512 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte.
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WATCHDOG TIMER (Cont'd) 10.1.8 Using Halt Mode with the WDG The following recommendations apply if Halt mode is used when the watchdog is enabled. - Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. 10.1.9 Interrupts None 10.1.10 Register Description CONTROL REGISTER (WDGCR) Read/Write Reset Value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
hardware after a reset. When WDGA = 1, the watchdog generates a reset when T6 reaches 0. 0: Watchdog Reset disabled 1: Watchdog Reset enabled Note: This bit is not used if the hardware watchdog reset option is enabled by option byte. Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A watchdog event is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
Bit 7 = WDGA Watchdog Reset Activation bit. This bit is set by software and only cleared by Table 23. Watchdog Timer Register Map and Reset Values
Address (Hex.) 0035h Register Label WDGCR Reset Value 7 WDGA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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10.2 TIMEBASE UNIT (TBU) 10.2.1 Introduction The Timebase unit (TBU) can be used to generate periodic interrupts. 10.2.2 Main Features 8-bit upcounter Programmable prescaler Period between interrupts: max. 8.1ms (at 8 MHz fCPU) Maskable interrupt 10.2.3 Functional Description The TBU operates as a free-running upcounter. When the TCEN bit in the TBUCSR register is set by software, counting starts at the current value of the TBUCV register. The TBUCV register is incremented at the clock rate output from the prescaler selected by programming the PR[2:0] bits in the TBUCSR register. When the counter rolls over from FFh to 00h, the OVF bit is set and an interrupt request is generated if ITE is set. The user can write a value at any time in the TBUCV register. 10.2.4 Programming Example In this example, timer is required to generate an interrupt after a delay of 1 ms. Assuming that fCPU is 8 MHz and a prescaler division factor of 256 will be programmed using the PR[2:0] bits in the TBUCSR register, 1 ms = 32 TBU timer ticks. In this case, the initial value to be loaded in the TBUCV must be (256-32) = 224 (E0h).
ld ld ld ld A, E0h TBUCV, A ; Initialize counter value A 1Fh ; TBUCSR, A ; Prescaler factor = 256, ; interrupt enable, ; TBU enable
Figure 25. TBU Block Diagram
MSB
LSB
TBU 8-BIT UPCOUNTER (TBUCV REGISTER)
TBU PRESCALER
fCPU
0
0
OVF
ITE TCEN PR2 PR1 PR0
TBUCSR REGISTER INTERRUPT REQUEST
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TIMEBASE UNIT (Cont'd) 10.2.5 Low Power Modes Mode WAIT HALT Description No effect on TBU TBU halted. Bit 5 = OVF Overflow Flag This bit is set only by hardware, when the counter value rolls over from FFh to 00h. It is cleared by software reading the TBUCSR register. Writing to this bit does not change the bit value. 0: No overflow 1: Counter overflow
Exit from Wait Yes Exit from Halt No
10.2.6 Interrupts
Interrupt Event Counter Overflow Event Event Flag OVF Enable Control Bit ITE
Note: The OVF interrupt event is connected to an interrupt vector (see Interrupts chapter). It generates an interrupt if the ITE bit is set in the TBUCSR register and the I-bit in the CC register is reset (RIM instruction). 10.2.7 Register Description TBU COUNTER VALUE REGISTER (TBUCV) Read/Write Reset Value: 0000 0000 (00h)
7 CV7 CV6 CV5 CV4 CV3 CV2 CV1 0 CV0
Bit 4 = ITE Interrupt enabled. This bit is set and cleared by software. 0: Overflow interrupt disabled 1: Overflow interrupt enabled. An interrupt request is generated when OVF=1. Bit 3 = TCEN TBU Enable. This bit is set and cleared by software. 0: TBU counter is frozen and the prescaler is reset. 1: TBU counter and prescaler running. Bit 2:0 = PR[2:0] Prescaler Selection These bits are set and cleared by software to select the prescaling factor.
PR2 PR1 PR0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Prescaler Division Factor 2 4 8 16 32 64 128 256
Bit 7:0 = CV[7:0] Counter Value This register contains the 8-bit counter value which can be read and written anytime by software. It is continuously incremented by hardware if TCEN=1. TBU CONTROL/STATUS REGISTER (TBUCSR) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 OVF ITE TCEN PR2 PR1 0 PR0
Bits 7:6 = Reserved. Forced by hardware to 0.
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TIMEBASE UNIT (Cont'd) Table 24. TBU Register Map and Reset Values
Address (Hex.) 0058h 0059h Register Label TBUCVR Reset Value TBUCSR Reset Value 7 CV7 0 0 0 6 CV6 0 0 0 5 CV5 0 OVF 0 4 CV4 0 ITE 0 3 CV3 0 TCEN 0 2 CV2 0 PR2 0 1 CV1 0 PR1 0 0 CV0 0 PR0 0
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10.3 16-BIT TIMER 10.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 10.3.2 Main Features Programmable prescaler: fCPU divided by 2, 4 or 8. Overflow status flag and maskable interrupt External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge 1 or 2 Output Compare functions each with: - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt 1 or 2 Input Capture functions each with: - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt Pulse width modulation mode (PWM) One pulse mode Reduced Power Mode 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 26. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 10.3.3 Functional Description 10.3.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): - Counter High Register (CHR) is the most significant byte (MS Byte). - Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). - Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 25 Clock Control Bits. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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16-BIT TIMER (Cont'd) Figure 26. Timer Block Diagram
ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE 8 low 8-bit buffer EXEDG 16 1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER 16 CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 16 INPUT CAPTURE REGISTER 2 16 8 high low 8 high 8 low 8 high 8 low 8 high 8 low 8
8 high
OUTPUT COMPARE CIRCUIT 6
EDGE DETECT CIRCUIT1
ICAP1 pin
EDGE DETECT CIRCUIT2
ICAP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 TIMD
OCMP1 pin OCMP2 pin
0
0 LATCH2
(Control/Status Register) CSR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(See note) TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)
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16-BIT TIMER (Cont'd) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence At t0 Read MS Byte Other instructions Read At t0 +t LS Byte Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set. - A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Returns the buffered
LS Byte is buffered
LS Byte value at t0
Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 10.3.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.
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16-BIT TIMER (Cont'd) Figure 27. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure 28. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure 29. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
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16-BIT TIMER (Cont'd) 10.3.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see figure 5).
ICiR MS Byte ICiHR LS Byte ICiLR
ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function select the following in the CR2 register: - Select the timer clock (CC[1:0]) (see Table 25 Clock Control Bits). - Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). And select the following in the CR1 register: - Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input or input with pullup without interrupt if this configuration is available).
When an input capture occurs: - ICFi bit is set. - The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 31). - A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One pulse Mode and PWM mode only Input Capture 2 can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh).
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16-BIT TIMER (Cont'd) Figure 30. Input Capture Block Diagram
ICAP1 pin ICAP2 pin EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register 1) CR1
IEDG1
(Status Register) SR IC2R Register IC1R Register
ICF1 ICF2 0 0 0
16-BIT 16-BIT FREE RUNNING COUNTER
(Control Register 2) CR2
CC1 CC0 IEDG2
Figure 31. Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: The rising edge is the active edge. FF03 FF01 FF02 FF03
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16-BIT TIMER (Cont'd) 10.3.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCiE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OCiR MS Byte OCiHR LS Byte OCiLR
- The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). - A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR =
Where:
t * fCPU
PRESC
t
fCPU
= Output compare period (in seconds) = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 25 Clock Control Bits) If the timer clock is an external clock, the formula is:
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. - Select the timer clock (CC[1:0]) (see Table 25 Clock Control Bits). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: - OCFi bit is set.
OCiR = t * fEXT
Where:
t
fEXT
= Output compare period (in seconds) = External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
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16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 33). This behaviour is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 34). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Figure 32. Output Compare Block Diagram
Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. The FOLVLi bits have no effect in both one pulse mode and PWM mode.
16-bit 16-bit
FREE RUNNING COUNTER
OC1E OC2E
CC1
CC0
(Control Register 2) CR2 (Control Register 1) CR1
OUTPUT COMPARE CIRCUIT 16-bit 16-bit
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
Latch 1
OCMP1 Pin OCMP2 Pin
OC1R Register
OCF1 OCF2 0 0 0
Latch 2
OC2R Register (Status Register) SR
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16-BIT TIMER (Cont'd) Figure 33. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure 34. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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16-BIT TIMER (Cont'd) 10.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use one pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 25 Clock Control Bits). One pulse mode cycle When event occurs on ICAP1 ICR1 = Counter OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 25 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) = External timer clock frequency (in hertz) fEXT When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 35). Notes: 1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.
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16-BIT TIMER (Cont'd) Figure 35. One Pulse Mode Timing Example
IC1R COUNTER ICAP1 OCMP1 OLVL2 OLVL1 OLVL2 01F8 FFFC FFFD FFFE 01F8 2ED0 2ED1 2ED2 2ED3 2ED3 FFFC FFFD
compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 36. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions
COUNTER 34E2 FFFC FFFD FFFE OCMP1 OLVL2
2ED0 2ED1 2ED2
34E2
FFFC
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
Note: On timers with only 1 Output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length.
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16-BIT TIMER (Cont'd) 10.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated. In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1). Procedure To use pulse width modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the opposite column. 3. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC2R register. 4. Select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock (CC[1:0]) (see Table 25 Clock Control Bits). Pulse Width Modulation cycle When Counter = OC1R
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 25 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 36) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.
OCMP1 = OLVL1
When Counter = OC2R
OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set
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16-BIT TIMER (Cont'd) 10.3.4 Low Power Modes
Mode WAIT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with "exit from HALT mode" capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.
HALT
10.3.5 Interrupts
Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event Event Flag ICF1 ICF2 OCF1 OCF2 TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 10.3.6 Summary of Timer modes
MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse Mode PWM Mode Input Capture 1 Yes Yes No No TIMER RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Yes Yes No Partially 2) Not Recommended1) Not Recommended3) No No
1) See note 4 in Section 10.3.3.5 One Pulse Mode 2) See note 5 in Section 10.3.3.5 One Pulse Mode 3) See note 4 in Section 10.3.3.6 Pulse Width Modulation Mode
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16-BIT TIMER (Cont'd) 10.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h)
7 0
Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
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16-BIT TIMER (Cont'd) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h)
7 0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bit 3, 2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 25. Clock Control Bits
Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 External Clock (where available) CC1 0 0 1 1 CC0 0 1 0 1
Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Bit 5 = OPM One Pulse Mode. 0: One Pulse Mode is not active. 1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.
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16-BIT TIMER (Cont'd) CONTROL/STATUS REGISTER (CSR) Read/Write (bits 7:3 read only) Reset Value: xxxx x0xx (xxh)
7 ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0 0
Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2 = TIMD Timer disable. This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled Bits 1:0 = Reserved, must be kept cleared.
Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register.
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16-BIT TIMER (Cont'd) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register.
7 0 LSB
COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event).
7 0 LSB
COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) Table 26. 16-Bit Timer Register Map and Reset Values
Address (Hex.) 0048h 0047h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h Register Label TCR1 Reset Value TCR2 Reset Value TCSR Reset Value TIC1HR Reset Value TIC1LR Reset Value TOC1HR Reset Value TOC1LR Reset Value TCHR Reset Value TCLR Reset Value TACHR Reset Value TACLR Reset Value TIC2HR Reset Value TIC2LR Reset Value TOC2HR Reset Value TOC2LR Reset Value 7 ICIE 0 OC1E 0 ICF1 MSB MSB MSB 1 MSB 0 MSB 1 MSB 1 MSB 1 MSB 1 MSB MSB MSB 1 MSB 0 6 OCIE 0 OC2E 0 OCF1 0 0 1 1 1 1 0 0 5 TOIE 0 OPM 0 TOF 0 0 1 1 1 1 0 0 4 FOLV2 0 PWM 0 ICF2 0 0 1 1 1 1 0 0 3 FOLV1 0 CC1 0 OCF2 0 0 1 1 1 1 0 0 2 OLVL2 0 CC0 0 TIMD 0 0 0 1 1 1 1 0 0 1 IEDG1 0 IEDG2 0 0 0 1 0 1 0 0 0 0 OLVL1 0 EXEDG 0 LSB LSB LSB 0 LSB 0 LSB 1 LSB 0 LSB 1 LSB 0 LSB LSB LSB 0 LSB 0
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10.4 SERIAL PERIPHERAL INTERFACE (SPI) 10.4.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 10.4.2 Main Features Full duplex synchronous transfers (on 3 lines) Simplex synchronous transfers (on 2 lines) Master or slave operation Six master mode frequencies (fCPU/4 max.) fCPU/2 max. slave mode frequency (see note) SS Management by software or hardware Programmable clock polarity and phase End of transfer interrupt flag Write collision, Master Mode Fault and Overrun flags Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 10.4.3 General Description Figure 37 shows the serial peripheral interface (SPI) block diagram. There are 3 registers: - SPI Control Register (SPICR) - SPI Control/Status Register (SPICSR) - SPI Data Register (SPIDR) The SPI is connected to external devices through 4 pins: - MISO: Master In / Slave Out data - MOSI: Master Out / Slave In data - SCK: Serial Clock out by SPI masters and input by SPI slaves - SS: Slave select: This input signal acts as a `chip select' to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master Device.
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 37. Serial Peripheral Interface Block Diagram
Data/Address Bus SPIDR Read Read Buffer Interrupt request
MOSI MISO
8-Bit Shift Register
7 SPIF WCOL OVR MODF 0
SPICSR
SOD SSM
0 SSI
SOD bit
Write
SS
SPI STATE CONTROL
7 SPIE
1 0
SCK
SPICR
0
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL SERIAL CLOCK GENERATOR
SS
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 38. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device reFigure 38. Single Master/ Single Slave Application
sponds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communication is possible). Four possible data/clock timing relationships may be chosen (see Figure 41) but master and slave must be programmed with the same timing mode.
MASTER MSBit LSBit MISO MISO MSBit
SLAVE LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
SPI CLOCK GENERATOR
SCK SS +5V
SCK SS
Not used if SS is managed by software
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 40) In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register. In Master mode: - SS internal must be held high continuously
In Slave Mode: There are two cases depending on the data/clock timing relationship (see Figure 39): If CPHA=1 (data latched on 2nd clock edge): - SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to VSS, or made free for standard I/O by managing the SS function by software (SSM= 1 and SSI=0 in the in the SPICSR register) If CPHA=0 (data latched on 1st clock edge): - SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 10.4.5.3).
Figure 39. Generic SS Timing Diagram
MOSI/MISO Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1)
Byte 1
Byte 2
Byte 3
Figure 40. Hardware/Software Slave Select Management SSM bit
SSI bit SS external pin
1 0
SS internal
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). To operate the SPI in master mode, perform the following steps in order (if the SPICSR register is not written first, the SPICR register setting (MSTR bit ) may be not taken into account): 1. Write to the SPICR register: - Select the clock frequency by configuring the SPR[2:0] bits. - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 41 shows the four possible configurations. Note: The slave must have the same CPOL and CPHA settings as the master. 2. Write to the SPICSR register: - Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. 3. Write to the SPICR register: - Set the MSTR and SPE bits Note: MSTR and SPE bits remain set only if SS is high). The transmit sequence begins when software writes a byte in the SPIDR register. 10.4.3.4 Master Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set 2. A read to the SPIDR register.
Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. 10.4.3.5 Slave Mode Operation In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the following actions: - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 41). Note: The slave must have the same CPOL and CPHA settings as the master. - Manage the SS pin as described in Section 10.4.3.2 and Figure 39. If CPHA=1 SS must be held low continuously. If CPHA=0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions. 10.4.3.6 Slave Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set. 2. A write or a read to the SPIDR register. Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 10.4.5.2).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 41). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge Figure 41. Data Clock Timing Diagram
Figure 41, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.
CPHA =1
SCK (CPOL = 1) SCK (CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
CPHA =0
SCK (CPOL = 1) SCK (CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.5 Error Flags 10.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: - The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the Device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the Device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read access to the SPICSR register while the MODF bit is set. 2. A write to the SPICR register. Notes: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device, the MODF bit can not be set, but in a multi master configuration the Device can be in slave mode with the MODF bit set. The MODF bit indicates that there might have been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset or return to an application default state.
10.4.5.2 Overrun Condition (OVR) An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte. When an Overrun occurs: - The OVR bit is set and an interrupt request is generated if the SPIE bit is set. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost. The OVR bit is cleared by reading the SPICSR register. 10.4.5.3 Write Collision Error (WCOL) A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. See also Section 10.4.3.2 Slave Select Management. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the CPU operation. The WCOL bit in the SPICSR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 42).
Figure 42. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SPICSR
RESULT
2nd Step
Read SPIDR
SPIF =0 WCOL=0
Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step 2nd Step Read SPICSR
RESULT
Read SPIDR
WCOL=0
Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.5.4 Single Master and Multimaster Configurations There are two types of SPI systems: - Single Master System - Multimaster System Single Master System A typical single master system may be configured, using a device as the master and four devices as slaves (see Figure 43). The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. Note: To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission.
For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register. Other transmission security methods can use ports for handshake lines or data bytes with command fields. Multi-Master System A multi-master system may also be configured by the user. Transfer of master control could be implemented using a handshake method through the I/O ports or by an exchange of code messages through the serial peripheral interface system. The multi-master system is principally handled by the MSTR bit in the SPICR register and the MODF bit in the SPICSR register.
Figure 43. Single Master / Multiple Slave Configuration
SS SCK Slave Device MOSI MISO
SS SCK Slave Device MOSI MISO
SS SCK Slave Device MOSI MISO
SS SCK Slave Device MOSI MISO
MOSI MISO SCK Master Device 5V SS Ports
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.6 Low Power Modes
Mode WAIT Description No effect on SPI. SPI interrupt events cause the Device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the Device is woken up by an interrupt with "exit from HALT mode" capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the Device.
SS pin or the SSI bit in the SPICSR register) is low when the Device enters Halt mode. So if Slave selection is configured as external (see Section 10.4.3.2), make sure the master drives a low level on the SS pin when the slave enters Halt mode. 10.4.7 Interrupts
Interrupt Event Event Flag Enable Control Bit Exit from Wait Yes SPIE Yes Yes Exit from Halt Yes No No
HALT
SPI End of TransSPIF fer Event Master Mode MODF Fault Event Overrun Error OVR
10.4.6.1 Using the SPI to wake-up the Device from Halt mode In slave configuration, the SPI is able to wake-up the Device from HALT mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware. Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately. Caution: The SPI can wake-up the Device from Halt mode only if the Slave Select signal (external
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 10.4.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh)
7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 0 SPR0
Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault or Overrun error occurs (SPIF=1, MODF=1 or OVR=1 in the SPICSR register) Bit 6 = SPE Serial Peripheral Output Enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 10.4.5.1 Master Mode Fault (MODF)). The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled Bit 5 = SPR2 Divider Enable. This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 27 SPI Master mode SCK Frequency. 0: Divider by 2 enabled 1: Divider by 2 disabled Note: This bit has no effect in slave mode. Bit 4 = MSTR Master Mode. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 10.4.5.1 Master Mode Fault (MODF)). 0: Slave mode 1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
Bit 3 = CPOL Clock Polarity. This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Bit 2 = CPHA Clock Phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Note: The slave must have the same CPOL and CPHA settings as the master. Bits 1:0 = SPR[1:0] Serial Clock Frequency. These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode. Note: These 2 bits have no effect in slave mode. Table 27. SPI Master mode SCK Frequency Serial Clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128 SPR2 1 0 0 1 0 0 SPR1 0 0 0 1 1 1 SPR0 0 0 1 0 0 1
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SERIAL PERIPHERAL INTERFACE (Cont'd) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h)
7 SPIF WCOL OVR MODF SOD SSM 0 SSI
Bit 2 = SOD SPI Output Disable. This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE=1) 1: SPI output disabled Bit 1 = SSM SS Management. This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section 10.4.3.2 Slave Select Management. 0: Hardware management (SS managed by external pin) 1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O) Bit 0 = SSI SS Internal Mode. This bit is set and cleared by software. It acts as a `chip select' by controlling the level of the SS slave select signal when the SSM bit is set. 0 : Slave selected 1 : Slave deselected DATA I/O REGISTER (SPIDR) Read/Write Reset Value: Undefined
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the Device and an external device has been completed. Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Bit 6 = WCOL Write Collision status (Read only). This bit is set by hardware when a write to the SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 42). 0: No write collision occurred 1: A write collision has been detected Bit 5 = OVR SPI Overrun error (Read only). This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 10.4.5.2). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected Bit 4 = MODF Mode Fault flag (Read only). This bit is set by hardware when the SS pin is pulled low in master mode (see Section 10.4.5.1 Master Mode Fault (MODF)). An SPI interrupt can be generated if SPIE=1 in the SPICR register. This bit is cleared by a software sequence (An access to the SPICSR register while MODF=1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bit 3 = Reserved, must be kept cleared.
The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Warning: A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Figure 37).
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SERIAL PERIPHERAL INTERFACE (Cont'd) Table 28. SPI Register Map and Reset Values
Address (Hex.) 0061h 0062h 0063h Register Label SPIDR Reset Value SPICR Reset Value SPICSR Reset Value 7 MSB x SPIE 0 SPIF 0 6 5 4 3 2 1 0 LSB x SPR0 x SSI 0
x SPE 0 WCOL 0
x SPR2 0 OVR 0
x MSTR 0 MODF 0
x CPOL x 0
x CPHA x SOD 0
x SPR1 x SSM 0
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10.5 USB INTERFACE 10.5.1 Introduction The USB Interface implements a high/full speed function interface between the USB and the ST7 microcontroller. It is a highly integrated circuit which includes the transceiver, USB controller and USB Data Buffer interface. No external components are needed apart from the external reference resistor. This USB function is based on ST PHY and Mentor MUSBHSFC USB2.0 Function controller. So parts of this specification are based on Mentor Graphics design documentation and used by permission. 10.5.2 Main Features USB Specification Version 2.0 Compliant On-Chip USB PHY Supports High/Full Speed USB Protocol 1 control endpoint with two 64 byte buffers 1 IN bulk / interrupt endpoint with 64 byte buffers 1 OUT bulk / interrupt endpoint with 64 byte buffers 1 IN bulk endpoint with a double packet buffering capability (2*512 bytes) 1 OUT bulk endpoint with a double packet buffering capability (2*512 bytes) Specific data transfer mode between USB buffer and MSCI for high transfer rate (does not require ST7 intervention) USB Suspend/Resume operations 10.5.3 Functional Description The block diagram in Figure 44, gives an overview of the USB interface hardware. For general information on the USB, refer to the "Universal Serial Bus Specifications" document available at http://www.usb.org. USB2.0 PHY The USB2.0 PHY serialises or deserialises the USB data in order to send them in parallel (16-bit) to the USB packet encoding/decoding block. Packet Encoding/Decoding CRC This block Encodes/Decodes the packet to be sent/to be received through the UTMI interface. It also performs frame formatting, including CRC generation and checking. Endpoint Control This block is composed of two controller state machines one for endpoint 0 and another for endpoints 1 and 2. CPU interface The CPU interface provides the access to the control and status registers and the USB buffers (FIFO) for each endpoint (through RAM controller block). It also generates an interrupt at the end of a reception / transmission or when suspend or resume is detected. The CPU interface is compatible with the VSIA standard BVCI (Basic Virtual Component Interface). RAM controller The RAM controller generates the SRAM control signals to access the endpoint FIFOs selected by the Endpoint Control block pointer information.
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Figure 44. USB Block Diagram USB ENDPOINT CONTROL
DM, DP VSSBL, VDDBL VSSC, VDDC VDD3 RREF USBIT
CPU
USB2.0 PHY
UTMI
Packet Encoding Decoding CRC
CPU IF
BVCI
VCI Access Controller
DMA
MSCI RAM Controller USB Buffers
10.5.4 USB2.0 PHY The USB2.0 PHY serialises or deserialises the USB data in order to send it in parallel (16-bit) to the USB packet encoding/decoding block through a UTMI compliant interface. The USB2.0 PHY requires only one external reference resistor (11.5k) to be connected to RREF chip input for process compensation. 10.5.5 USB buffers The USB buffers are as follows:
two 64 byte buffers for control transfer on endpoint 0 two 64 byte buffers, one for IN and one for OUT bulk / interrupt transfer on endpoint 1 two double 512 byte buffers, one for IN (2*512) and one for OUT (2*512) bulk transfer on endpoint 2 This buffer is implemented by a 2304 byte SRAM. To access to these endpoint buffers three addresses are available, one for each endpoint. Writing to these addresses loads data into the IN buffer of the corresponding endpoint. Reading from these addresses unloads data from the OUT buffer of the corresponding endpoint.
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USB INTERFACE (Cont'd) 10.5.6 Register Description The registers are divided in three groups: - common USB registers (function controller control and status registers) - indexed registers (endpoint control and status registers) - buffer register access - end of suspend detection registers 10.5.6.1 Common USB registers POWER REGISTER (PWRR) Read/Write Reset Value: 0010 0000 (20h)
7 0 SCON HSE HSM RST RSM SUSM 0 ESUS M
Bit 4 = HSM HS Mode (Read Only). This bit is set by hardware when the function has successfully negotiated the HS mode during the Reset phase. 0: FS mode 1: HS mode Bit 3 = RST Reset (Read Only). This bit is set by hardware while reset signalling is present on the bus. 0: No Reset on the bus 1: Reset on the bus Bit 2 = RSM Resume. This bit is set by software to generate Resume signalling to wake-up from suspend mode. 0: No Resume generated 1: Resume generated Software should clear this bit after 10ms (and before 15ms) to end Resume signalling. Bit 1 = SUSM Suspend Mode (Read Only). This bit is set by hardware when suspend mode is entered. It is cleared when software reads the interrupt register or sets the RSM bit. 0: Suspend mode inactive 1: Suspend mode active Bit 0 = ESUSM Enable Suspend Mode. This bit is set by software to enable the SUSPENDM UTMI signal. 0: SUSPENDM signal not activated 1: SUSPENDM signal activated When this bit is not set suspend mode will be detected but the SUSPENDM signal will remain high (active low).
Bit 7 = Reserved, forced by hardware to 0. Bit 6 = SCON Soft Connect/Disconnect. This bit is set by software to enabled the USB D+ / D- lines. 0: D+/D- tri-stated 1: D+/D- lines enabled Bit 5 = HSE HS Enable. This bit is set by software to negotiate for high speed mode when the device is reset by the hub. 0: Full Speed mode 1: High Speed mode
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USB INTERFACE (Cont'd) FUNCTION ADDRESS (FADDR) Read/Write Reset Value: 0000 0000 (00h)
7 UPD FAD6 FAD5 FAD4 FAD3 FAD2 FAD1 0 FAD0
INTERRUPT OUT REGISTER (ITOUTR) Read only. Reset value: 0000 0000 (00h)
7 0 0 0 0 0 EP2O EP1O 0 0
Bit 7 = UPD Update (Read Only). Set when FADDR is written. Cleared when the new address takes effect (at the end of the current transfer). Bits 6:0 = FAD[6:0] Function address. These bits are written by software with the function address provided by the SET_ADDRESS standard device request (see Universal Serial Bus Specification Revision 2.0, Chapter 9). INTERRUPT IN REGISTER (ITINR) Read only. Reset value: 0000 0000 (00h)
7 0 0 0 0 0 EP2I EP1I 0 EP0
This register indicates which OUT Endpoint interrupt is currently pending. Bit 7:3 = Reserved. Bit 2 = EP2O Endpoint 2 OUT. 0: No OUT interrupt on endpoint 2 1: OUT interrupt on endpoint 2 Bit 1 = EP1O Endpoint 1 OUT. 0: No OUT interrupt on endpoint 1 1: OUT interrupt on endpoint 1 Bit 0 = Reserved. Note: all active interrupts are cleared when this register is read. INTERRUPT IN ENABLE REGISTER (ITINER) Read/Write. Reset value: 0000 0111 (07h)
7 0 0 0 0 0 EP2IE EP1IE 0 EP0E
This register indicates which IN endpoint (1 or 2) interrupt is currently pending. It also indicates whether the Endpoint 0 interrupt is currently active Bit 7:3 = Reserved. Bit 2 = EP2I Endpoint 2 IN flag. 0: No IN interrupt on endpoint 2 1: IN interrupt on endpoint 2 Bit 1 = EP1I Endpoint 1 IN flag. 0: No IN interrupt on endpoint 1 1: IN interrupt on endpoint 1 Bit 0 = EP0 Endpoint 0 flag. 0: No interrupt on endpoint 0 1: Interrupt on endpoint 0 Note: all pending interrupt flags are cleared when this register is read.
This register indicates which IN Endpoint (1 or 2) interrupt is enabled. It also indicates whether the Endpoint 0 interrupt is enabled. Bit 7:3 = Reserved. Bit 2 = EP2IE Endpoint 2 IN Enabled. 0: IN interrupt on endpoint 2 disabled 1: IN interrupt on endpoint 2 enabled Bit 1 = EP1IE Endpoint 1 IN Enabled. 0: IN interrupt on endpoint 1 disabled 1: IN interrupt on endpoint 1 enabled
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Bit 0 = EP0E Endpoint 0 Enabled. 0: interrupt on endpoint 0 disabled 1: Interrupt on endpoint 0 enabled INTERRUPT OUT ENABLE REGISTER (ITOUTER) Read/Write. Reset value: 0000 0110 (06h)
7 0 0 0 0 0 EP2OE EP1OE 0 0
Bit 2 = RSTE Reset Enable. 0: Reset interrupt disabled 1: Reset interrupt enabled Bit 1 = RSME Resume Enable. 0: Resume interrupt disabled 1: Resume interrupt enabled Bit 0 = SUSPE Suspend Enable. 0: Suspend interrupt disabled 1: Suspend interrupt enabled INTERRUPT USB REGISTER (ITUSBR) Read only. Reset value: 0000 0000 (00h)
7 0 0 0 0 SOF RST RSM SUSP
This register indicates which OUT Endpoint interrupt is enabled. Bit 7:3 = Reserved. Bit 2 = EP2OE Endpoint 2 OUT Enable. 0: OUT interrupt on endpoint 2 disabled 1: OUT interrupt on endpoint 2 enabled Bit 1 = EP1OE Endpoint 1 OUT Enable. 0: OUT interrupt on endpoint 1 disabled 1: OUT interrupt on endpoint 1 enabled Bit 0 = Reserved. INTERRUPT USB ENABLE REGISTER (ITUSBER) Read/Write. Reset value: 0000 0110 (06h)
7 0 0 0 0 SOFE RSTE RSME 0 SUSP E
0
This register indicates which USB interrupts are currently pending. Bit 7:4 = Reserved. Bit 3= SOF Start Of Frame Interrupt. 0: No SOF interrupt 1: SOF interrupt pending Bit 2 = RST Reset Interrupt. 0: No Reset interrupt 1: Reset interrupt pending Bit 1 = RSM Resume Interrupt. 0: No Resume interrupt 1: Resume interrupt pending Bit 0 = SUSP Suspend Interrupt. 0: No Suspend interrupt 1: Suspend interrupt pending Note: all pending interrupts are cleared when this register is read.
These bits are written by software to enable / disable the USB interrupts. Bit 7:4 = Reserved. Bit 3= SOFE Start Of Frame Enable. 0: SOF interrupt disabled 1: SOF interrupt enabled
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USB INTERFACE (Cont'd) FRAME NUMBER REGISTER MSB (FRNBRM) Read Only. Reset value: 0000 0000 (00h)
7 0 0 0 0 0 FN10 FN9 0 FN8
Bit4 = FHS Force High-Speed. Software can set this bit to force the USB device into High-speed mode when it receives a USB reset. Bit 3 = TPAK Test Packet. Software can set this bit to enter the Test_Packet test mode. In this mode, the USB device- in highspeed mode - repetitively transmits on the bus a 53-byte test packet. Note: The 53-byte test packet must be loaded into the Endpoint 0 FIFO before the test mode is entered. Bit 2 = TK Test K. Software can set this bit to enter the Test_K test mode. In this mode, the USB device- in highspeed mode - transmits a continuous K on the bus. Bits 1 = TJ Test J. Software can set this bit to enter the Test_J test mode. In this mode, the MUSBHSFC - in highspeed mode - transmits a continuous J on the bus. Bits 0= TSE0N Test SE0 NAK. Software can set this bit to enter the Test_SE0_NAK test mode. In this mode, the USB Device remains in high-speed mode and responds to any valid IN token with a NAK. INDEX REGISTER (INDEXR) Read/Write Reset value: 0000 0000 (00h)
7 0 0 0 0 0 0 IND1 IND0
This register indicates the MSB of the last frame number received. Bit 7:3 = Reserved. Bit 2:0 = FN[10:8] Frame number MSB. FRAME NUMBER REGISTER LSB (FRNBRL) Read Only. Reset value: 0000 0000 (00h)
7 FN7 FN6 FN5 FN4 FN3 FN2 FN1 0 FN0
This register indicates the LSB of the last frame number received. Bit 7:0 = FN[7:0] Frame number LSB. TEST MODE REGISTER (TSTMODER) Read/Write Reset value: 0000 0000(00h)
7 0 0 FFS FHS TPAK TK TJ 0 TSE0N
This register is used to put the USB device into one of the four test modes described in the USB 2.0 specification. It is not used in normal operation. Bit 7:6 = Reserved. Bit 5 = FFS Force Full-Speed. Software can set this bit to force the USB device into Full-speed mode when it receives a USB reset.
0
This register is written by software to determine which endpoint control/status registers are addressed at 10h to 19h. Bits [7:2] = Reserved. Bit 1:0= IND[1:0] Index.
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IND1 0 0 1 1
IND0 0 1 0 1
Meaning Endpoint 0 addressing Endpoint 1 addressing Endpoint 2 addressing -
Each IN endpoint and each OUT endpoint has its own set of control/status registers. Only one set of IN control/status and one set of OUT control/status registers appear in the memory map at any one time. Before accessing an endpoint's control/status registers, the endpoint number should be written to the Index register to ensure that the correct control/status registers appear in the memory map 10.5.6.2 Indexed registers Note: The action of the following registers is undefined if the selected endpoint has not been configured. IN MAX PACKET REGISTER MSB (INMAXPRM) Read/Write Reset value: 0000 0000 (00h)
7 0 0 0 0 0 IMP10 IMP9 0 IMP8
Bits 7:0 = IMP[7:0] IN Max Packet. INMAXPR are registers that define the maximum amount of data that can be transferred through the selected IN endpoint in a single frame / microframe (High-speed transfers). There is an INMAXPR register for each IN endpoint (except Endpoint 0). The value written to the INMAXPRx registers should match the wMaxPacketSize field of the Standard Endpoint Descriptor for the associated endpoint (see Universal Serial Bus Specification Revision 2.0, Chapter 9). A mismatch could cause unexpected results. The total amount of data represented by the value written to these registers (maximum payload x maximum number of transactions) must not exceed the FIFO size for the IN endpoint, and should not exceed half the FIFO size if double-buffering is required. If these registers are changed after packets have been sent from the endpoint, the IN endpoint FIFO should be completely flushed (using the FLFI bit in INCSRL) after writing the new value to these registers. IN CONTROL STATUS REGISTER MSB (INCSRM) INCSRM is the MSB of a register that provides control and status bits for IN transactions through the currently-selected endpoint. There is an INCSRM register for each IN endpoint (not including Endpoint 0). For endpoint 0: This register is reserved and returns 00h. For endpoint 1 and 2: Read/Write Reset value: 0000 0000 (00h)
7 ASET o 0 DMAE FDT 0 0 0 0
This register defines the most significant byte of the maximum payload transmitted in a single transaction. Bits 7:3 = Reserved. Bit 2:0= IMP[10:8] IN Max Packet. IN MAX PACKET REGISTER LSB (INMAXPRL) Read/Write Reset value: 0000 0000 (00h)
7 IMP7 IMP6 IMP5 IMP4 IMP3 IMP2 IMP1 0 IMP0
This register defines the lowest significant byte of the maximum payload transmitted in a single transaction.
Bit 7 = ASET Auto Set. If the CPU sets this bit, IPR will be automatically set when data of the maximum packet size (value in INMAXPR) is loaded into the IN FIFO. If a packet of less than the maximum packet size is loaded, IPR will have to be set manually.
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Bit 6:5 = Reserved. Bit 4 = DMAE DMA Enable 0: DMA request for the IN endpoint disabled 1: DMA request for the IN endpoint enabled. Bit 3 = FDT Force Data Toggle The CPU sets this bit to force the endpoint's IN data toggle to switch after each data packet is sent regardless of whether an ACK was received. 0: Data toggle not forced 1: Data toggle forced Bits 2:0= Reserved. IN CONTROL STATUS REGISTER LSB (INCSRL) INCSRL is the LSB of a register that provides control and status bits for IN transactions through the currently-selected endpoint. There is an INCSRL register for each IN endpoint (not including Endpoint 0). For endpoint 0 this control status register is common to SETUP, IN or OUT transactions. For endpoint 0 (CSR0): CSR0 appears in the memory map when the Index register is set to 0. It is used for all control/status of Endpoint 0. For details of how to service device requests to Endpoint 0, see Section 12.4.10: `Endpoint 0 Handling'. Read/Write Reset value: 0000 0000 (00h)
7 SSE SOPR SDST SE DE STST IPR 0 OPR
matically. Bit 4 = SE Setup End (Read Only) This bit will be set when a control transaction ends before the DE bit has been set. An interrupt will be generated and the FIFO flushed at this time. The bit is cleared by software writing a 1 to the SSE bit. Bit 3 = DE Data End Software sets this bit: - when setting IPR bit for the last data packet. - when clearing OPR bit after unloading the last data packet. - when setting IPR bit for a zero length data packet. It is cleared automatically. Bit 2 = STST Sent Stall This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Bit 1 = IPR In Packet Ready Software sets this bit after loading a data packet into the FIFO. It is cleared automatically when the data packet has been transmitted. An interrupt is generated when the bit is cleared. Bit 0 = OPR Out Packet Ready (Read Only) This bit is set when a data packet has been received. An interrupt is generated when this bit is set. Software clears this bit by setting the SOPR bit. For endpoint 1 and 2: Read/Write Reset value: 0000 0000 (00h)
7 0 CDT STST SDST FLFI UNDR FINE 0 IPR
Bit 7 = SSE Serviced Setup End. Software writes a 1 to this bit to clear the SE bit. SSE is cleared automatically. Bit 6 = SOPR Serviced OUT Packet Ready. Software writes a 1 to this bit to clear the OPR bit. SOPR is cleared automatically Bit 5 = SDST Send Stall. Software writes a 1 to this bit to terminate the current transaction. The STALL handshake will be transmitted and then this bit will be cleared auto-
Bit 7 = Reserved. Bit 6 = CDT Clear Data Toggle. Software writes a 1 to this bit to reset the endpoint IN data toggle to 0. Bit 5 = STST Sent Stall This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the IPR bit is cleared. Software should clear this bit.
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Bit 4 = SDST Send Stall The CPU writes a 1 to this bit to issue a a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Bit 3 = FLFI Flush FIFO (Self clearing) Software writes a 1 to this bit to flush the next packet to be transmitted from the endpoint IN FIFO. The FIFO pointer is reset and the IPR bit is cleared. Note: If the FIFO contains two packets, FlushFIFO will need to be set twice to completely clear the FIFO Bit 2 = UNDR Under Run This bit is set when a NAK is returned in response to an IN token. Software should clear this bit. Bit 1 = FINE FIFO not empty This bit is set when there is at least 1 packet in the IN FIFO. Bit 0 = IPR In Packet Ready Software sets this bit after loading a data packet into the FIFO. It is cleared automatically when the data packet has been transmitted. If the FIFO is double-buffered, it is also automatically cleared when there is space for a second packet in the FIFO. An interrupt is generated (if enabled) when this bit is cleared. OUT MAX PACKET REGISTER MSB (OUTMAXPRM) Read/Write Reset value: 0000 0000 (00h)
7 0 0 0 0 0 0 OMP1 OMP9 OMP8 0
OUT MAX PACKET REGISTER LSB (OUTMAXPRL) Read/Write Reset value: 0000 0000 (00h)
7 0
OMP7 OMP6 OMP5 OMP4 OMP3 OMP2 OMP1 OMP0
This register defines the least significant byte of the maximum payload transmitted in a single transaction. Bits 7:0 = OMP[7:0] OUT Max Packet. OUTMAXPR are registers that define the maximum amount of data that can be transferred through the selected OUT endpoint in a single frame / microframe (High-speed transfers). There is an OUTMAXP register for each OUT endpoint (except Endpoint 0). The value written to the OUTMAXPRx registers should match the wMaxPacketSize field of the Standard Endpoint Descriptor for the associated endpoint (see Universal Serial Bus Specification Revision 2.0, Chapter 9). A mismatch could cause unexpected results. The total amount of data represented by the value written to these registers (maximum payload x maximum number of transactions) must not exceed the FIFO size for the OUT endpoint, and should not exceed half the FIFO size if doublebuffering is required. OUT CONTROL STATUS REGISTER MSB (OUTCSRM) OUTCSRM is the MSB of a register that provides control and status bits for OUT transactions through the currently-selected endpoint. Read/Write Reset value: 0000 0000 (00h)
7 0 o DMAE DNY DMAM 0 0 0
This register defines the most significant byte of the maximum payload transmitted in a single transaction. Bits 7:3 = Reserved.
ACLR
Bit 2:0= OMP[10:8] OUT Max Packet. Bit 7 = ACLR Auto Clear. If software sets this bit then the OPR bit will be au-
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tomatically cleared when a packet of OUTMAXP bytes has been unloaded from the OUT FIFO. When packets of less than the maximum packet size are unloaded, OPR will have to be cleared manually. Bit 6 = Reserved. Bit 4 = DMAE DMA Enable 0: DMA request for the OUT endpoint disabled 1: DMA request for the OUT endpoint enabled. Bit 4 = DNY Disable Nyet Software sets this bit to disable the sending of NYET handshakes. When set, all successfully received OUT packets are ACK'd including at the point at which the FIFO becomes full. Note: This bit only has effect in High-speed mode. In this mode it should be set for all Interrupt endpoints. Bit 3 = DMAM DMA Mode Two modes of operation are supported: In DMA Mode 0 a DMA request is generated for all received packets, together with an interrupt (if enabled); In DMA Mode 1 a DMA request (but no interrupt) is generated for OUT packets of size OUTMAXP bytes and an interrupt (but no DMA request) is generated for OUT packets of any other size. DMAM is set by software to select the DMA mode. 0: DMA Mode 0 1: DMA Mode 1 Bit 2:0= Reserved. OUT CONTROL STATUS REGISTER LSB (OUTCSRL) OUTCSRL is the LSB of a register that provides control and status bits for OUT transactions through the currently-selected endpoint. Read/Write Reset value: 0000 0000 (00h)
7 CDT STST SDST FLFI 0 0 FIFU 0 OPR
Bit 7 = CDT Clear Data Toggle. Software writes a 1 to this bit to reset the endpoint OUT data toggle to 0. Bit 6 = STST Sent Stall This bit is set when a STALL handshake is transmitted. Software should clear this bit. Bit 5= SDST Send Stall Software writes a 1 to this bit to terminate the current transaction. The STALL handshake will be transmitted and then this bit will be cleared automatically. Bit 4= FLFI Flush FIFO (Self clearing) Software writes a 1 to this bit to flush the next packet to be read from the endpoint OUT FIFO. Note: If the FIFO contains two packets, FlushFIFO will need to be set twice to completely clear the FIFO. Bit 3:2 = Reserved. Bit 1 = FIFU FIFO full flag This bit is set when no more packets can be loaded into the OUT FIFO. FIFU is cleared by hardware. Bit 0 = OPR OUT Packet Ready flag This bit is set when a data packet has been received. Software should clear this bit when the packet has been unloaded from the OUT FIFO. An interrupt is generated (if enabled) when the bit is set. OUT COUNT REGISTER MSB (OUTCNTRM) Read Only Reset value: 0000 0000 (00h)
7 0 0 0 OC12 OC11 OC10 OC9 0 OC8
OUTCNTRM is the MSB register that holds the number of received data bytes in the packet in the OUT FIFO. Note: The value returns changes as the contents of the FIFO change and is only valid while OPR bit in the OUTCSRL register is set.
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Bits 7:5 = Reserved. Bit 4:0= OC[12:8] OUT Count. OUT COUNT REGISTER LSB (OUTCNTRL) Read/Write Reset value: 0000 0000 (00h)
7 OC7 OC6 OC5 OC4 OC3 OC2 OC1 0 OC0
EOS STATUS REGISTER (EOSSR) Read / Write Reset Value: 0000 0000 (00h)
7 LS1 LS0 0 0 0 0 0 0 EOS
Bit 7 = LS1 Line State 1 flag. This bit is read only by software 0: LS1 is at 0 (D-=0) 1: LS1 is at 1 (D-=1) Bit 6 = LS0 Line State 0 flag. This bit is read only by software 0: LS0 is at 0 (D+=0) 1: LS0 is at 1 (D+=1) Bit 5:1 = Reserved. Bit 0 = EOS End Of Suspend. This bit is set by hardware and cleared by software. 0: No EOS interrupt occurred 1: EOS interrupt occurred Note: A parasitic EOS bit set can occur at device start up so it is mandatory to clear this bit before enabling the interrupt (by setting EOSE). EOS CONTROL REGISTER (EOSCR) Read / Write Reset Value: 0000 0000 (00h)
7 LSE 0 0 0 0 UPO CPO 0 EOSE
OUTCNTRL is the LSB register that holds the number of received data bytes in the packet in the OUT FIFO. Notes: The value returned changes as the contents of the FIFO change and is only valid while OPR bit in the OUTCSRL register is set. For endpoint 0 and 1 only OUTCNTRL has to be read (OUTCNTRM is reserved and returns 00h). Bits 7:0 = OC[7:0] OUT Count. 10.5.6.3 FIFO register addressing This address range provides 3 addresses for CPU access to the FIFOs for each endpoint. Writing to these addresses loads data into the IN FIFO for the corresponding endpoint. Reading from these addresses unloads data from the OUT FIFO for the corresponding endpoint.
Address 21h 23h 25h
R/W R W R W R W
FIFO accessed Endpoint 0 OUT / SETUP Endpoint 0 IN Endpoint 1 OUT Endpoint 1 IN Endpoint 2 OUT Endpoint 2 IN
Bit 7 = LSE Line State Enable. This bit is set and cleared by software. 0: Line State flag disabled 1: Line State flag enabled. Bit 6:3 = Reserved. Bit 2 = UPO USB2 Phy Off. This bit is set and cleared by software. When the USB part is not used the PHY can be stopped completely to remove useless consumption. 0: USB2 PHY enabled 1: USB2 PHY disabled. Bit 1 = CPO Compensation Cell Off. This bit is set and cleared by software. Set this bit to decrease the consumption (for instance before entering in suspend / halt mode) by removing the IOs active slew rate control PVT compensation.
10.5.6.4 End of suspend detection register This register controls a specific end of suspend block that is able to wake-up the ST7 when the clocks are stopped.
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0: Compensation cell enabled 1: Compensation cell disabled. Bit 0 = EOSE End Of Suspend Enabled. This bit is set and cleared by software to enable/ disable the End Of Suspend interrupt generation. 0: EOS interrupt disabled 1: EOS interrupt enabled Note: before enabling EOS interrupt (setting EOSE bit), it is advised to clear the EOS bit of EOSSR register to avoid any parasitic interrupt. 10.5.7 Programming consideration This section describes how to control the USB device. 10.5.7.1 Soft Connect/Disconnect The UTMI interface between the PHY and the USB controller can be switched between normal mode and non-driving mode by setting/clearing bit 6 of the Power register (PWRR). When the Soft Connect/Disconnect bit is set to 1, the PHY is placed in its normal mode and the D+/ D- lines of the USB bus are enabled. At the same time, the USB controller is placed in `Powered' state, in which it will not respond to any USB signalling except a USB reset. 10.5.8 USB reset When a reset condition is detected on the USB, the USB controller performs the following actions: Sets FAddr to 0. Sets Index to 0. Flushes all endpoint FIFOs. Clears all control/status registers. Enables all interrupts, except Suspend. Generates a Reset interrupt. When the software receives a Reset interrupt, it should close any open pipes and wait for bus enumeration to begin. 10.5.9 Suspend /Resume When the USB device sees no activity on the USB for 3 ms it will generate a Suspend interrupt. It is up to the software to decide what to disable when the USB is in Suspend mode. Note: To decrease the consumption, refer to the Halt mode description chapter, section 5.3 on page 27.
Software may perform "Remote Wake-up" by setting the Resume bit in the Power register (bit 2). The USB device will then send Resume signalling on the USB to wake up the hub. The USB may exit Suspend mode by sending Resume signalling on the bus, this detection could be performed differently if the clocks are active or not in the device. 10.5.9.1 Remote wake-up If the USB device is in Suspend mode and the software wants to initiate a remote wake-up, it should write to the Power register to set the Resume bit (bit 2) to 1. Of course if the clocks are stopped, it will need an external event (ST7 external interrupt) to restart the clocks. Software should leave this bit set for approximately 10 ms (minimum of 2 ms, a maximum of 15 ms) then reset it to 0. By this time the hub should have taken over driving Resume signalling on the USB. Note: No Resume interrupt is generated when software initiates a remote wake-up. 10.5.9.2 Clock active during suspend If the Enable Suspend Mode bit in the Power register (bit 0) is set when a Suspend interrupt is generated, the UTM will be put into Suspend mode by the SUSPENDM line. The USB controller will, however, remain active and therefore can detect when Resume signalling occurs on the USB. It will then bring the UTM out of Suspend mode and generate a Resume interrupt. 10.5.9.3 Clock inactive during suspend When a Suspend interrupt is received, software may put the device in Halt mode by executing the ST7 halt instruction. In this case a specific block "end of Suspend Block" will track any change on UTM linestate signals. If a linestate toggles the EOS block generates an USB End Of Suspend Interrupt to wake-up the ST7 from Halt. After the clocks are restored the USB device will detect the wake-up event (Resume or Reset). 10.5.10 Endpoint 0 handling Endpoint 0 is the main control endpoint of the core. As such, the routines required to service Endpoint 0 are more complicated than those required to service other endpoints. The software is required to handle all the Standard Device Requests that may be received via End-
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point 0. These are described in the Universal Serial Bus Specification, Revision 2.0, Chapter 9. The protocol for these device requests involves different numbers and types of transaction per transfer. To accommodate this, application software needs to take a state machine approach to command decoding and handling. The Standard Device Requests can be divided into three categories: Zero Data Requests (in which all the information is included in the command), Write Requests (in which the command will be followed by additional data), and Read Requests (in which the device is required to send data back to the host). This section looks at the sequence of events that the software must perform to process the different types of device request. 10.5.10.1 Endpoint 0 Service Routine An Endpoint 0 interrupt is generated: When the core sets the OPR bit (CSR0) after a valid token has been received and data has been written to the FIFO. When the core clears the IPR bit (CSR0) after the packet of data in the FIFO has been successfully transmitted to the host. When the core sets the STST bit (CSR0) after a control transaction is ended due to a protocol violation. When the core sets the SE bit (CSR0) because a control transfer has ended before DE (CSR0) is set. Whenever the Endpoint 0 service routine is entered, the software must first check to see if the current control transfer has been ended due to either a STALL condition or a premature end of control transfer. If the control transfer ends due to a STALL condition, the STST bit is set. If the control transfer ends due to a premature end of control transfer, the SE bit is set. In either case, the software should abort processing the current control transfer and set the state to IDLE. 10.5.10.2 Error Handling A control transfer may be aborted due to a protocol error on the USB, the host prematurely ending the transfer, or if the function controller software wishes to abort the transfer (e.g. because it cannot process the command). The USB controller will automatically detect protocol errors and send a STALL packet to the host under the following conditions:
1. Host sends more data during the OUT Data phase of a write request than was specified in the command. This condition is detected when the host sends an OUT token after the DE bit (CSR0) has been set. 2. Host requests more data during the IN Data phase of a read request than was specified in the command. This condition is detected when the host sends an IN token after the DE bit in the CSR0 register has been set. 3. Host sends more than MaxP data bytes in an OUT data packet. 4. Host sends a non-zero length DATA1 packet during the STATUS phase of a read request. When the USB controller has sent the STALL packet, it sets the STST bit (CSR0) and generates an interrupt. When the software receives an Endpoint 0 interrupt with the STST bit set, it should abort the current transfer, clear the SentStall bit, and return to the IDLE state. If the host prematurely ends a transfer by entering the STATUS phase before all the data for the request has been transferred, or by sending a new SETUP packet before completing the current transfer, then the SE bit (CSR0) will be set and an Endpoint 0 interrupt generated. When the software receives an Endpoint 0 interrupt with the SE bit set, it should abort the current transfer, set the SSE bit (CSR0), and return to the IDLE state. If the OPR bit (CSR0) is set this indicates that the host has sent another SETUP packet and the software should then process this command. 10.5.11 Bulk IN Endpoint A Bulk IN endpoint is used to transfer non-periodic data from the function controller to the host. Three optional features are available for use with a Bulk IN endpoint: Double packet buffering If the value written to the INMAXPR register is less than, or equal to, half the size of the FIFO allocated to the endpoint, double packet buffering will be automatically enabled. When enabled, up to two packets can be stored in the FIFO awaiting transmission to the host. DMA If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint is able to accept another packet in its FIFO. This feature is used to allow transfer to the MSCI without ST7 intervention in order to allow high speed transfer to/ from the USB controller. AutoSet
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When the AutoSet (INCSRM) feature is enabled, the IPR bit (INCSRL.bit0) will be automatically set when a packet of INMAXPR bytes has been loaded into the FIFO. This is particularly useful when DMA is used to load the FIFO as it avoids the need for any processor intervention when loading individual packets during a large Bulk transfer. 10.5.12 Bulk OUT Endpoint A Bulk OUT endpoint is used to transfer non-periodic data from the host to the function controller. Three optional features are available for use with a Bulk OUT endpoint: Double packet buffering If the value written to the OUTMAXP register is less than, or equal to, half the size of the FIFO allocated to the endpoint, double packet buffering will be automatically enabled. When enabled, up to two packets can be stored in the FIFO. DMA If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint has a packet in its FIFO. This feature can be used to allow an external DMA controller to unload packets from the FIFO without processor intervention. AutoClear When the AutoClear feature is enabled, the OPR bit (OutCSR.D0) will be automatically cleared when a packet of OUTMAXP bytes has been unloaded from the FIFO. This is particularly useful when DMA is used to unload the FIFO as it avoids the need for any processor intervention when unloading individual packets during a large Bulk transfer.
10.5.13 Interrupt IN Endpoint An Interrupt IN endpoint is used to transfer periodic data from the function controller to the host. An Interrupt IN endpoint uses the same protocol as a Bulk IN endpoint and can be used the same way. However, though DMA can be used, it offers little benefit as Interrupt endpoints are usually expected to transfer all their data in a single packet. Interrupt IN endpoints also support one feature that Bulk IN endpoints do not, in that they support continuous toggling of the data toggle bit. This feature is enabled by setting the FDT bit in the INCSRM register. When this bit is set to 1, the USB controller will consider the packet as having been successfully sent and toggle the data bit for the endpoint, regardless of whether an ACK was received from the host. 10.5.14 Interrupt OUT endpoint An Interrupt OUT endpoint is used to transfer periodic data from the host to a function controller. An Interrupt OUT endpoint uses almost the same protocol as a Bulk OUT endpoint and can be used the same way. The one difference is that Interrupt endpoints do not support PING flow control. This means that the USB controller should never respond with a NYET handshake, only ACK/NAK/ STALL. To ensure this, the DNY bit in the OUTCSRM register should be set to 1 to disable the transmission of NYET handshakes in High-speed mode. Though DMA can be used with an Interrupt OUT endpoint, it generally offers little benefit as Interrupt endpoints are usually expected to transfer all their data in a single packet.
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10.5.15 Low Power modes
Mode WAIT No effect on USB.
Description USB interrupt events cause the device to exit from WAIT mode. USB registers are frozen. In halt mode, the USB is inactive. USB operations resume when the MCU is woken up by an interrupt with "exit from halt capability" or by an event on the USB line in case of suspend. This event will generate an EOS interrupt which will wake-up from halt mode.
HALT
10.5.16 Interrupts
Interrupt Event Start Of Frame USB Reset Resume Suspend EP0 EP1 IN EP2 IN EP1 OUT EP2 OUT USB End Of Suspend
Event Flag SOF RST RSM SUSP EP0 EP1I EP2I EP1O EP2O EOS
Enable Con- Exit From trol Bit Wait SOFE RSTE RSME SUSPE EP0E EP1IE EP2IE EP1OE EP2OE EOSE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Exit From Halt No No No No No No No No No Yes
Note: The USB End Of Suspend interrupt event is connected to a single interrupt vector (EOS) with exit from halt capability (wake-up). The other interrupt events are connected to another interrupt vec-
tor: USB interrupt (USB). They generate an interrupt if the corresponding enable control bit is set and the interrupt mask bits (I0, I1) in CC register are reset (RIM instruction).
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Table 29. USB Register Map and Reset Values
Address (Hex.)
0000h
Register Name
PWRR Reset Value FADDR Reset Value ITINR Reset Value ITOUTR Reset Value ITINER Reset Value ITOUTER Reset Value ITUSBER Reset Value ITUSBR Reset Value FRNBRM Reset Value FRNBRL Reset Value TSTMODER Reset Value INDEXR Reset Value INMAXPRM Reset Value INMAXPRL Reset Value INCSRM IND=0 Reset Value INCSRM IND=1 or 2 Reset Value INCSRL (CSR0) IND=0 Reset Value INCSRL IND=1 or 2 Reset Value OUTMAXPRM Reset Value
7
6
SCON 0 FAD6 0 0
5
HSE 1 FAD5 0 0
4
HSM 0 FAD4 0 0
3
RST 0 FAD3 0 0
2
RSM 0 FAD2 0 EP2I 0 EP2O 0 EP2IE 1 EP2OE 1 RSTE 1 RST 0 FN10 0 FN2 0 TK 0 0 IMP10 0 IMP2 0 0
1
SUSM 0 FAD1 0 EP1I 0 EP1O 0 EP1IE 1 EP1OE 1 RSME 1 RSM 0 FN9 0 FN1 0 TJ 0 IND1 0 IMP9 0 IMP1 0 0
0
ESUSM 0 FAD0 0 EP0 0 0 EP0E 1 0 SUSPE 0 SUSP 0 FN8 0 FN0 0 TSE0N 0 IND0 0 IMP8 0 IMP0 0 0
0 UPD 0 0
0001h
0003h
0005h
0
0
0
0
0
0007h
0
0
0
0
0
0009h
0
0
0
0
0 SOFE 0 SOF 0 0 FN3 0 TPAK 0 0
000Ah
0
0
0
0
000Bh
0
0
0
0
000Ch
0 FN7 0 0
0 FN6 0 0
0 FN5 0 FFS 0 0
0 FN4 0 FHS 0 0
000Dh
000Eh
000Fh
0
0
0010h
0 IMP7 0 0 ASET 0 SSE 0 0
0 IMP6 0 0
0 IMP5 0 0
0 IMP4 0 0 DMAE 0 SE 0 SDST 0 0
0 IMP3 0 0 FDT 0 DE 0 FLFI 0 0
0011h
0012h
0 SOPR 0 CDT 0 0
0 SDST 0 STST 0 0
0 STST 0 UNDR 0 OMP10 0
0 IPR 0 FINE 0 OMP9 0
0 OPR 0 IPR OMP8 0
0013h
0014h
0
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Address (Hex.)
0015h
Register Name
OUTMAXPRL Reset Value OUTCSRM Reset Value OUTCSRL Reset Value OUTCNTRM Reset Value OUTCNTRL Reset Value EOSSR Reset Value EOSCR Reset Value
7
OMP7 0 ACLR 0 CDT 0 0 OC7 0 LS1 0 LSE 0
6
OMP6 0 0 STST 0 0 OC6 0 LS0 0 0
5
OMP5 0 DMAE 0 SDST 0 0 OC5 0 0
4
OMP4 0 DNY 0 FLFI 0 OC12 0 OC4 0 0
3
OMP3 0 DMAM 0 0 OC11 0 OC3 0 0
2
OMP2 0 0
1
OMP1 0 0 FIFU 0 OC9 0 OC1 0 0
0
OMP0 0 0 OPR 0 OC8 0 OC0 0 EOS 0 EOSE 0
0016h
0017h
0 OC10 0 OC2 0 0
0018h
0019h
005Fh
0060h
0
0
0
0
0
Notes: 1. The USB registers can also be accessed by the MSCI through the VCI interface (see section 16 on page 126). 10.5.17 IMPORTANT NOTES EP1/EP2 configuration With the ST7267, it is not possible to deactivate EP1 or EP2. If not used, it must be configured in STALL condition.
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11 MASS STORAGE COMMUNICATION INTERFACE (MSCI)
11.1 INTRODUCTION The MSCI is a complete system designed to handle various communication protocols. The MSCI is built around a 16-bit RISC core capable of addressing up to 4K bytes of program memory, up to 8K bytes of data memory and a maximum of 32 internal registers The MSCI system provides three communication interfaces: VCI Generic Parallel Interface Standard I/O Controller Figure 45. MSCI Block Diagram All the MSCI system is controlled by the ST7 through a dedicated interface which manages: program memory upload MSCI soft reset MSCI core PC forcing
Mass Storage Communication Interface
VCI INTERFACE
USB INTERFACE
CPU
REGISTERS
COMMUNICATION INTERFACE
MSCI I/O PORT
I/O CONTROLLER
DATA
PROGRAM
ST7 INTERFACE DPRAM MSCI CODE RAM
ST7 BUS
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12 MSCI REGISTER & MEMORY MAP
As shown in Figure 46, the MSCI is able to address 1KWords of program memory, 2.5KWords of data memory and 32 registers. . Figure 46. MSCI Memory Map
MSCI Data Space 000h ST7 Space 1100h MSCI Program Space 000h ST7 Space 1100h
The detail of the MSCI register map is given in Table 30. For a description of the ST7 memory map refer to section 3 on page 17
MSCI CODE RAM 1 KWords DPRAM 2.5 KWords
7FFh 9FFh 24FFh 3FFh 18FFh
Reserved
Reserved
FFFh
00h
Registers
1Fh
Each MSCI address corresponds to a 16-bit word Each ST7 address corresponds to a 8-bit word
Table 30. MSCI Hardware Register Map
Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h VCI Block Register Label R0 R1 R2 R3 DP0 DP1 DP2 DP3 P1DRO P1DRI P1DDR P2DRO P2DRI P2DDR VCR VSR VFDR VTAR Register Name General Purpose CPU Register 0 General Purpose CPU Register 1 General Purpose CPU Register 2 General Purpose CPU Register 3 Data memory Pointer 0 Data memory Pointer 1 Data memory Pointer 2 Data memory Pointer 3 Port 1 Data Register Output Port 1 Data Register Input Port 1 Data Direction Register Port 2 Data Register Output Port 2 Data Register Input Port 2 Data Direction Register VCI Control Register VCI Status Register VCI FIFO Data Register VCI Target Address Register Reset Status 0000h 0000h 0000h 0000h 000h 000h 000h 000h 0000h 0000h 0000h 0000h 0000h 0000h 02F0h 0001h 0000h 0000h Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R/W
MSCI CPU
CPU DP
Port 1
Port 2
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Address 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Block
Register Label PNDR PFDR PCR1 PCR2 PSR ELP1 ECP1 ELP2 ECP2 RCSR RDFR REFR
Register Name Parallel interface Number of Data Register Parallel interface FIFO Data Register Parallel interface Control Register 1 Parallel interface Control Register 2 Parallel interface Status Register ECC Line Parity 1 ECC Column Parity 1 ECC Line Parity 2 ECC Column Parity 2 Reed Solomon control status register Reed Solomon decoder FIFO register Reed Solomon Encoder FIFO register Reserved
Reset Status 0000h 0000h 007Fh 0000h 0009h FFFFh 00FFh FFFFh 00FFh 4000h 0000h 0000h 0000h 0000h
Remarks R/W R/W R/W R/W R R R R R R/W R/W R R R
Parallel Interface
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13 MSCI CENTRAL PROCESSING UNIT
13.1 INTRODUCTION The CPU has a full 16-bit architecture. Ten internal registers allow efficient 16-bit data manipulation. The CPU is able to execute 39 basic instructions. It features 6 main addressing modes and can address 8 internal registers. 13.2 MAIN FEATURES

13.3 CPU REGISTERS The 10 CPU registers are shown in the programming model in Figure 47. Following a CALL instruction, R0, R1, DP0, PC and Status are saved. They are restored following a RET instruction. GP Registers(R0, R1, R2, R3). These 16-bit general purpose registers are used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations. Data Pointer Registers (DP0, DP1, DP2, DP3). These 12-bit registers are used to handle data memory addressing. As the result, the MSCI core can access up to 8Kbyte of data memory. Program Counter (PC). The program counter is a 11-bit register used to store the address of the next instruction to be executed by the CPU. It is automatically refreshed after each processed instruction. As a result, the MSCI core can access up to 4Kbyte of program memory.
Enable executing 39 basic instructions 6 main addressing modes Four 16-bit general purpose registers Four 12-bit data pointers One 11-bit program counter One 5-bit status register
Figure 47. MSCI CPU Registers
15 R0 15 R1 15 R2 15 R3 11 DP0 11 DP1 11 DP2 11 DP3 10 PC 4 0 0 0 0 0 0 0 0 0 0
R0 R1 R2 R3
DP0 DP1 DP2 DP3 PC Program Counter Status Register
BS AI Cd Z C
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MSCI CENTRAL PROCESSING UNIT (Cont'd) STATUS REGISTER (STATUS) Read / Write Reset Value: 0000 0000 0001 1000 (0018h)
15 BS AI Cond Z 0 C
The 5-bit Status register contains: - two configuration flags handling special Wait on Bit State (WBS) instruction, and post-incremented/ decremented Data RAM Load management. - three status flags Condition, Zero and Carry. Bit 15:5 = Reserved. Configuration flags Bit 4 = BS Bit Set. When set to 1, this bit indicates that the Wait Bit State (WBS) instruction will wait until the selected bit is set. Otherwise, it will wait until the selected bit is reset. This bit is set and cleared by software using WOSet and WORst instructions. 0: WBS instruction will wait until the polled bit is reset 1: WBS instruction will wait until the polled bit is set Bit 3 = AI Auto Increment. When set to 1, this bit indicates that the CPU is in post-increment mode. If reset, the CPU is in postdecrement mode (See LD instructions in the MSCI CPU Programming Manual). This bit is set and cleared by software using AutoINC and AutoDEC instructions. 0: Auto-decrement mode 1: Auto-Increment mode
Status flags Bit 2 = Cond Condition. When set to 1, this bit indicates that the result of the last comparison is true. This bit is set and cleared by hardware or software using SECond and CLCond instructions. 0: Last comparison result is false 1: Last comparison result is true Bit 1 = Z Zero. When set to 1, this bit indicates that the result of the last ALU operation is zero. This bit can be set and cleared by hardware or software using SEZ and CLZ instructions. 0: Last ALU operation result is not zero 1: Last ALU operation result is zero Bit 0 = C Carry. When set to 1, this bit indicates that a carry borrow out of the ALU occurred during the last arithmetic operation. This bit is also affected during, shift instructions. See ADD, ADDC, SUB, SUBC instructions. This bit can be set and cleared by hardware or software using SEC and CLC instructions. 0: No carry 1: Carry borrow out
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14 MSCI ST7 INTERFACE
14.1 INTRODUCTION The MSCI ST7 interface provides three main system control functions: Controlling the MSCI from the ST7 MSCI Interrupt Requests to ST7 MSCI Code RAM Upload The MSCI ST7 Interface block diagram is shown in Figure 48. 14.2 FUNCTIONAL DESCRIPTION The MSCI ST7 Interface provides three main functions between ST7 core and MSCI system. Figure 48. MSCI ST7 Interface Block Diagram 14.2.1 ST7 Control of the MSCI The ST7 can control the MSCI through the MCR (MSCI Control Register). It allows the ST7 to: Reset the whole MSCI system by setting the SFTR bit. Force the MSCI core program counter to the specified values in the MPCL and MPCM (MSCI Program Counter LSB and MSCI Program Counter MSB) registers by setting the PCR bit. Continue the program executed by the MSCI after it has been self-stopped with an internal STOP instruction by writing a'1' in the GO bit.
ST7 BUS
MSCI CODE RAM
RAM CONTROL
CORE CONTROL
MSCI BUS
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MSCI ST7 INTERFACE (Cont'd) 14.2.2 Interrupt generation from MSCI to ST7 Each time the MSCI core executes a STOP instruction it stops itself and the STOP bit in the MSR (MSCI Status Register) is set. An interrupt is generated if the STPIE bit in the MCR (MSCI Control Register) is set. This feature allows the MSCI core to interrupt the ST7 each time it completes a function ended by a STOP instruction. The ITR MSCI CPU instruction sets the ITR bit in the MSR register without stopping the MSCI cpu. An interrupt is generated if the STPIE bit in the MCR (MSCI Control Register) is set. 14.2.3 Program RAM upload The MSCI ST7 interface provides read and write access to the program memory of the MSCI core. The RAM is mapped in the memory array of the ST7 core like any other memory but access to this memory is protected depending on the state of the MSCI system.
To access the memory with the ST7 the MSCI system must be in PC or Soft reset, i.e the PCR or SFTR bits of the MCR (MSCI Control Register) are set. In this state, the RAMLD bit of the MCR (MSCI Control Register) can be set to switch the Data RAM access from the MSCI to the ST7. When the RAMLD bit in the MCR (MSCI Control Register) is reset, the ST7 cannot access the MSCI program memory: - a write access by the ST7 to the MSCI program memory has no effect. - a read access by the ST7 to the MSCI program memory returns $00 value. When the RAMLD bit in the MCR (MSCI Control Register) is set, the ST7 can read or write from/ into this memory. Reading can be performed randomly at any address of the RAM. Writing into this memory can only be performed by writing pairs of bytes starting with the even address byte followed by the next higher byte.
Figure 49. Typical ST7 flow for MSCI program memory update
MSCI core stopped force SFTR or PCR on MSCI by writing to MCR
ST7 core can control MSCI program Memory partial update of 16-bit memory word with incorrect value Update of 16-bit memory word with correct value
Set RAMLD flag by by writing to MCR
store value in program memory at address 2n
store value in program memory at address 2n+1
n<=n+2
plugin code loaded in MSCI program memory ?
NO
YES
ST7 core can no longer control the MSCI program memory Reset RAMLD flag by writing to MCR
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MSCI ST7 INTERFACE (Cont'd) 14.2.4 ST7 Write Access to MSCI Code RAM The ST7 can only write in MSCI RAM when the RAMLD bit of the MCR (MSCI Control Register) is set. To set this flag, the MSCI core must be stopped either by a PC reset or a soft reset. Due to 8/16-Bit conversion, writing in the MSCI program memory must be done in a specific sequence: At each even access the 8-bit value is stored in a temporary register (but the 16-bit RAM word is updated with an incorrect temporary value). At each odd access the 16-bit value (made of the 8-bit value stored previously in the temporary register for the LSB and of the 8-bit of the even access for the MSB) is written in the memory. For this reason an odd number of bytes cannot be written in this memory and the bytes must always
be written in ascending order (from a low address to higher addresses) 14.2.4.1 ST7 Read Access to MSCI Code RAM Reading from the ram is possible only when the RAMLD bit of the MCR (MSCI Control Register) is set. To set this flag, the MSCI core must be stopped either by a PC reset or a soft reset. Read access by the st7 core can be performed randomly at any address of the RAM.
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MSCI ST7 INTERFACE (Cont'd) 14.2.5 Example Control Flow Figure 50 gives an example of an application flow showing the ST7 controlling the MSCI. Figure 50. Example of ST7 Controlling MSCI
ST7 CORE
Reset state : MSCI SFTR=1
MSCI CORE
Set RAMLD bit in the MCR register Load program memory with ST7 core. MSCI CORE FROZEN Reset RAMLD bit and enable STPIE stop interrupt in the MCR register
Load new set of functions in the MSCI program Memory
Reset the SFTR bit in the MCR register
Start the MSCI and wait for the end of the MSCI function ST7 core waiting for MSCI interrupt (or executing software not related to the MSCI )
MSCI executing the plugin loaded by st7 in its program memory
STOP instruction executed
Check the result of MSCI function
ST7 MSCI interrupt routine
Clear Interrupt and launch new MSCI function by changing the MSCI PC to select the address of the function to execute
Clear IT by writing 1 in the MSR clear CSTP bit Change MSCI PC Force MSCI PC Reset Release MSCI PC Reset
MSCI CORE FROZEN
MSCI executing another function of the plugin available in MSCI program Memory
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MSCI ST7 INTERFACE (Cont'd) 14.2.6 ST7 Register Description ALL THESE REGISTERS ARE IN THE ST7 MEMEMORY MAP AND CANNOT BE ACCESSED BY THE MSCI CORE MSCI CONTROL REGISTER (MCR) Read / Write Reset Value: 0000 0001 (01h)
7 ITRIE STPIE GO RAMLD PCR 0 SFTR
MSCI STATUS REGISTER (MSR) Read / Write Reset Value: 0000 0000 (00h)
7 ITR STP CITR 0 CSTP
Bit 7:6 = Reserved Bit 5 = ITR MSCI CORE ITR flag. This bit is set by MSCI software and cleared by a PC reset or a soft reset or by writing a '1' in the CITR bit in ST7 software. 0: MSCI ITR flag not set 1: MSCI ITR flag set by an internal ITR instruction. Bit 4 = STP MSCI CORE Stop flag. This bit is set by MSCI software and cleared by a PC reset or a soft reset or by writing a '1' in the CSTP bit in ST7 software 0: MSCI stop flag not set 1: MSCI stop flag set by an internal STOP instruction Bit 3:2 = Reserved Bit 1 = CITR Clear ITR flag. This bit is set by ST7 software to clear the MSCI ITR flag and interrupt and reset by hardware. It is always read as '0'. 0: No effect 1: Clears MSCI ITR flag and interrupt if pending Bit 0 = CSTP Clear Stop flag. This bit is set by ST7 software to clear the MSCI STOP flag and interrupt and reset by hardware. It is always read as '0'. 0: No effect 1: Clears MSCI STOP flag and interrupt if pending Note: To set the RAMLD bit when PCR=0 and SFTR=0, two write accesses to MCR register are needed. The first access must set either the SFTR bit or the PCR bit to enable write access to RAMLD bit. The second write access can set the RAMLD bit. Except in emulation mode when MSCI is stopped by emulator. To clear the PCR bit or the SFTR bit when RAMLD bit is set, two write accesses to MCR register are needed. The first access to reset the RAMLD bit. The second write access to clear PCR bit or SFTR bit. This must be done also in emulation mode.
Bit 7:6 = Reserved Bit 5 = ITRIE ITR Interrupt Enable. This bit is set and cleared by ST7 software 0: ITR interrupt disabled 1: ITR interrupt enabled Bit 4 = STPIE Stop Interrupt Enable. This bit is set and cleared by ST7 software 0: STOP interrupt disabled 1: STOP interrupt enabled Bit 3 = GO Go. This bit is set by ST7 software and cleared by hardware. It is always read as '0'. It generates a pulse to launch the MSCI after it has been selfstopped by an internal STOP instruction. 0: No effect 1: Generate a starting pulse Bit 2 = RAMLD RAM Load. This bit is set and cleared by ST7 software. The MSCI must be under PC or Soft reset before starting a read or write sequence. It can be written only when PCR or SFTR is set (or when MSCI is stopped by emulator in emulation mode) See Section 14.2.4 and Section 14.2.4.1 0: RAM access from ST7 disabled 1: RAM access from ST7 enabled Bit 1 = PCR Program Counter Reset. This bit is set and cleared by ST7 software. It can be written only when RAMLD is cleared. 0: MSCI program counter reset not forced 1: MSCI program counter forced to MPCM & MPCL value. Bit 0 = SFTR Soft Reset. This bit is set and cleared by ST7 software. It can be written only when RAMLD is cleared. 0: MSCI system reset not forced 1: MSCI system under reset.
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MSCI ST7 INTERFACE (Cont'd) MSCI PROGRAM COUNTER MSB (MPCM) Read / Write Reset Value: 0000 0000 (00h)
7 PC10 PC9 0 PC8
MSCI CRC MSB (MCRCM) Read Reset Value: 0000 0000 (00h)
7 0
CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8
Bit 7:3 = Reserved Bit 2:0 = PC[10:8] Program Counter (MSB). MSCI core Program Counter MSB. These bits are set and cleared by ST7 software and are loaded in the MSCI core program counter at each PC reset or Soft reset. MSCI PROGRAM COUNTER LSB (MPCL) Read / Write Reset Value: 0000 0000 (00h)
7 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0
Bit 7:0 = CRC[15:8] CRC (MSB). MSCI cyclic redundancy code. This code provides a signature of the MSCI code execution (read only). It is generated by MSCI core. It is reset by SOFT Reset. MSCI CRC MSB (MCRCL) Read Reset Value: 0000 0000 (00h)
7 0
CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0
Bit 7:0 = PC[7:0] Program Counter (LSB). MSCI core Program Counter LSB. These bits are set and cleared by ST7 software and are loaded in the MSCI core program counter at each PC reset or Soft reset.
Bit 7:0 = CRC[7:0] CRC (LSB). MSCI cyclic redundancy code. This code provides a signature of the MSCI code execution (read only). It is generated by MSCI core. It is reset by SOFT Reset.
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MSCI ST7 INTERFACE (Cont'd) 14.2.7 Low Power modes
Mode WAIT No effect on MSCI. MSCI interrupt events cause the device to exit from WAIT mode. MSCI registers are frozen. In halt mode, the MSCI is inactive. MSCI operations resume when the MCU is woken up by an interrupt with "exit from halt capability". Description
HALT
14.2.8 Interrupts
Interrupt Event MSCI STOP MSCI ITR Event Flag STP ITR Enable Con- Clear Inter- Exit From trol Bit rupt Bit Wait STPIE ITRIE CITR CSTP Yes Yes Exit From Halt No No
Note: Both stop and ITR interrupts are connected to the same interrupt vector. They generate an interrupt if the corresponding enable control bit is set and the interrupt mask bits (I0, I1) in CC register
are reset (RIM instruction)
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Table 31. MSCI ST7 Interface User Register Map and Reset Values
Address (Hex.)
0069h
Register Name
MCR Reset Value MSR Reset Value MPCM Reset Value MPCL Reset Value MCRCH Reset Value MCRCL Reset Value
7
6
5
ITRIE 0 ITR 0 0 PC5 0 CRC13 0 CRC5 0
4
STPIE 0 STP 0 0 PC4 0 CRC12 0 CRC4 0
3
GO 0 0
2
RAMLD 0 0 PC10 0 PC2 0 CRC10 0 CRC2 0
1
PCR 0 CITR 0 PC9 0 PC1 0 CRC9 0 CRC1 0
0
SFTR 1 CSTP 0 PC8 0 PC0 0 CRC8 0 CRC0 0
0
0
006Ah
0
0
006Bh
0 PC7 0 CRC15 0 CRC7 0
0 PC6 0 CRC14 0 CRC6 0
0 PC3 0 CRC11 0 CRC3 0
006Ch
006Ch
006Dh
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15 MSCI I/O CONTROLLER
15.1 INTRODUCTION The MSCI I/O ports can be configured in different functional modes: - data transfer through digital inputs and outputs and for specific pins: - alternate input/output signals for the parallel interface. Each of the two I/O ports contains 16 pins. Each pin can be programmed independently as digital input or digital output. 15.2 FUNCTIONAL DESCRIPTION Each port has 3 main registers: - Data Register Out (DRO) - Data Register Input (DRI) - Data Direction Register (DDR) Each I/O pin may be programmed using the corresponding register bits in the DDR register: bit X corresponding to pin X of the port. The same correspondence is used for the DRO and DRI registers. The DRO and DDR registers can be read and written by the MSCI core. The DRI register is an image corresponding to the logic level on the I/OO pin and can be read by the MSCI core (read only register). The MSCI I/O control block diagram is shown in Figure 51. 15.2.1 Input mode The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DRI register returns the digital value applied to the external I/O pin. In this mode writing the DRO register has no effect on the pad. However the values are written in the DRO register and if the DDR register is set to output mode, the value on the port will be the value written previously in the DRO register. 15.2.2 Output mode The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DRO register applies this digital value to the I/O pin through the latch. In this mode reading the DRI register returns the digital value applied to the external I/O pin. 15.2.3 Alternate functions When an on-chip peripheral is configured to use a pin in output mode, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from the parallel interface, the I/O pin is automatically configured in output mode when needed. There are two cases depending of the type of signal: - Control signals are configured using the CS bit in the PCR2 register. - Data signals are configured when the DIR bit in the PCR1 register is set in output mode and data transmission is on going. When the signal is going to the parallel interface (input mode), the I/O pin has to be configured in input mode by the standard I/O programming to avoid conflicts.
Figure 51. I/O Port General Block Diagram (When I/Os are dedicated to MSCI)
MSCI I/O Controller
ALTERNATE ENABLE ALTERNATE OUTPUT DRO
I/O
1 0
VDD P-BUFFER VDD
DDR DRO SEL
DATA BUS
VDD 1
PULL-UP CONDITION
PAD
DDR SEL
0 N-BUFFER CMOS SCHMITT TRIGGER
DRI SEL
MSCI CLOCK
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MSCI I/O PORTS (Cont'd) 15.3 I/O SHARING BETWEEN ST7 AND MSCI If MSCI I/Os are shared between the MSCI I/O controller and the ST7 I/O controller, the MSCI outputs are connected to alternate function of the ST7 I/O logic and the MSCI output enable signals are connected to the alternate enable inputs of the ST7 I/O logic. When ST7 configures a shared I/O in Input floating mode, the MSCI I/O logic can directly control this I/ O. When ST7 configures an I/O in output mode, the MSCI can control this port in output mode by setting the corresponding DDR bit because it has the priority on I/O control. Consequently, the value on the port is forced by the corresponding bit of the MSCI DRO register (of port 1 or port 2). However the MSCI can't force this I/O to be in input mode.
Figure 52. I/O Port General Block Diagram (when MSCI I/Os are shared with ST7I/ O Logic)
MSCI I/O Controller
ALTERNATE ENABLE ALTERNATE OUTPUT DRO ST7 I/O control
I/O
1 0 ALTERNATE OUTPUT See ST7 I/O control description for more information VDD 1 DDR SEL 0 N-BUFFER ALTERNATE OUTPUT ENABLE PULL-UP CONDITION
VDD P-BUFFER VDD
DDR DRO SEL
DATA BUS
PAD
DRI SEL
CMOS SCHMITT TRIGGER
MSCI CLOCK
MSCI DDR
ST7 DDR
EFFECT ON PORT Port in input mode. Can be read by both MSCI through DRI register and ST7 through DR register. Port in output mode, value forced by ST7 DR register. Port in output mode, value forced by MSCI DRO register. Port in output mode, value forced by MSCI DRO register.
0
0
0
1
1
0
1
1
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MSCI I/O PORTS (Cont'd) 15.3.1 Register Description DATA REGISTER OUTPUT (DRO) Read / Write Reset Value: 0000 0000 0000 0000 (0000h)
15 D15 D14 D13 D12 D11 D10 D9 8 D8 7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 15:0 = D[15:0] Data Output. Data output on the I/Os when they are configured in output mode. DATA REGISTER INPUT (DRI) Read Reset Value: xxxx xxxx xxxx xxxx (xxxxh) The reset value depends on the value forced externally on the pins)
15 D15 D14 D13 D12 D11 D10 D9 8 D8 7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 15:0 = D[15:0] Data Input. Input of the I/Os regardless of whether they are configured in input or output mode. The value read is not directly the value on the PAD but the value DATA DIRECTION REGISTER OUTPUT (DDR) Read / Write Reset Value: 0000 0000 0000 0000 (0000h)
15 Dir15 Dir14 Dir13 Dir12 Dir11 Dir10 Dir9 8 Dir8 7
sampled twice to avoid metastability problems. For this reason, the value read from the DRI register is the value that was present on the PAD 2 MSCI clock cycles before the current time.
0 Dir6 Dir5 Dir4 Dir3 Dir2 Dir1 Dir0
Dir7
Bit 15:0 = Dir[15:0] Direction. Define the I/O configuration: input mode or output mode. 0: Input mode 1: Output mode
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16 MSCI VCI INTERFACE
16.1 INTRODUCTION The MSCI VCI Interface handles communications between the MSCI and a VCI Target. The protocol used is based on the B-VCI specification. The MSCI always acts as initiator 16.2 MAIN FEATURES

Based on the B-VCI specification 4 Registers - Control register - Status register - Target address register - 8-word Data FIFO (for transmission and reception)
Figure 53. MSCI VCI Interface Block Diagram
MSCI BUS
INTERFACE
RTX REGISTERS
START FINISHED
VCI CORE FIFO (8 words) BUFFER
MSCI VECTORED BUS
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MSCI VCI INTERFACE (Cont'd) 16.3 FUNCTIONAL DESCRIPTION The VCI Interface is designed to handle the Basic VCI protocol. Figure 54 shows a state diagram of the logic described below, following the device from state to state. Configuration When the VCI Interface is disabled (bit VCIEN in the VCR (VCI Control Register) is reset), the VCI Interface can be configured. The configuration consist of: write to the NP bits of the VCR to define the number of 8-Word packets for reading in burst mode if the VCI interface is configured in burst mode. Figure 54. VCI Interface State Diagram Idle
Read from the FIFO
Write from the FIFO
defining through the bit 8BM of the VCR if the VCI sends and receive 8-bit or 16-bit data when not configured in burst mode. selecting with bit BM of the VCR if the message is one word long (normal mode) or is composed of n packets of m words.
Idle state Once the interface is configured, it can be enabled by setting the bit VCIEN of the VCR. The VCI Interface state machine is in idle state, waiting for the MSCI CPU to read or write to the FIFO to start the communication.
Read packet
FIFO Empty & VCI Request ended
Wait for FIFO full
FIFO full
Buffer to FIFO
VCI Request ended & Not Burst mode OR VCI Request ended & Burst mode & Message ended
FIFO to buffer
VCI Request ended & Burst Mode & Message not ended
Buffer loaded
Wait for FIFO empty
Send packet
VCI Request ended & FIFO full
FIFO empty
VCI Request ended
VCI Request ended & Writing in the FIFO
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MSCI VCI INTERFACE (Cont'd) Read / Write operation in normal mode Normal mode means that the BM bit of the VCR is reset: burst mode is not enabled. To read a single word or byte message, once the MSCI VCI Interface enabled and in idle state, the MSCI CPU just has to read the word in the VFDR (VCI FIFO Data Register).The MSCI CPU is stopped until the data is available from the target address. The target address is given by the VTAR (VCI Target Address Register). To write a single word or byte message, once the MSCI VCI Interface in idle state, the MSCI CPU just has to write the word to transmit in the VFDR (VCI FIFO Data Register) if the FIFO is empty. The word is automatically transmitted to the VCI Target. Thus, from a software point of view, the FIFO register acts like any other register in normal mode for both Read and Write operations. Note: after a write operation, the user has to wait for the end of the communication by polling the CP bit of the VSR before stopping the VCI interface with the VCIEN bit of the VCR. If not, communication may be cut leading to an incorrect VCI message transmission. Read operation in burst mode A complete message of N 8-Word packets can be read from the register pointed to by VTAR (VCI Target Address Register). The message size, N, is defined by NP bits in the VCR (VCI Control Register). When the MSCI VCI Interface is on and in idle state, the MSCI CPU reads the words in the VFDR (VCI FIFO Data Register). Once the FIFO is emp16.4 ERROR MANAGEMENT The MSCI VCI Interface does not perform any error management. ty, it is reloaded with the content of the VCI buffer which contains the next packet. If the packet is not available, the CPU is stopped until it arrives. After the last word of the last packet has been read, the LWR bit of the VSR (VCI Status Register) is set. Write operation in burst mode A 8-Word packet can be written to the register pointed to by VTAR (VCI Target Address Register). When the MSCI VCI Interface is on and in idle state, the MSCI CPU writes the word to transmit in the VFDR (VCI FIFO Data Register). Once the FIFO is full (8 words have been written), its content is automatically transmitted to the VCI buffer which send on the VCI bus. The FIFO becomes empty and the bit FE of the VCR (VCI Control Register) is set, and thus, the CPU loads the next 8 words in the FIFO. Because of the FIFO structure, loads (LD instruction) must not be used with immediate value. Note: after a write operation, the user has to wait for the end of the communication by polling the CP bit of the VSR before stopping the VCI interface with the VCIEN bit of the VCR. If not, communication may be cut leading to an incorrect VCI message transmission. Both read or write can be performed through: the regular MSCI bus: as in normal mode, the FIFO register acts as a regular register. the MSCI vectored bus: the complete FIFO is read/write in one CPU cycle to/from an other FIFO in the MSCI system. This is done using the LDv instruction.
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MSCI VCI INTERFACE (Cont'd) 16.4.1 MSCI VCI Interface Registers VCI CONTROL REGISTER (VCR) Read / Write Reset Value: 0000 0010 1111 0000 (02F0h)
15 8 EP<1:0> 7 NP<3:0> 8BM BM 0 VCIEN
Bit 15:8 = Reserved. Bit 9:8 = EP[1:0] End Point Index Bits. Index register for selecting the USB endpoint status and control registers. Bit 7:4 = NP Number of Packets. Defines the number of 8-Word packets in a message from 2 to 32. Refer to Table 32. This bit is set and cleared by software. It can only be set when the VCI interface is disabled. Table 32. Number of Packets vs. NP value
NP No. of value Pkts
0h 1h 2h 3h 2 4 6 8
Bit 3 = Reserved Bit 2 = 8BM 8-Bit Mode. Select if the VCI communication is 8-bit or 16-bit through the value of the VCI BE lines. This bit is set and cleared by software. It can only be set when the VCI interface is disabled. 0: 16-bit mode: VCI BE = "11" 1: 8-bit mode: VCI BE = "01" Bit 1 = BM Burst Mode. This bit is set and cleared by software. It can only be set when the VCI interface is disabled. 0: Word 1: Burst Bit 0 = VCIEN VCI EN. This bit is set and cleared by software. To prevent spurious communication breaks, the user must reset this bit when no communication is in progress i.e the CP bit of the VSR register is '0'. 0: VCI Interface is disabled 1: VCI Interface is enabled
NP No. of NP No. of NP No. of value Pkts value Pkts value Pkts
4h 5h 6h 7h 10 12 14 16 8h 9h Ah Bh 18 20 22 24 Ch Dh Eh Fh 26 28 30 32
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MSCI VCI INTERFACE (Cont'd) VCI STATUS REGISTER (VSR) Read / Write Reset Value: 0000 0000 0000 0001 (0001h)
15 8 7 UDRO UDRI LWR CP FF 0 FE
Bit 15:6 = Reserved. Bit 5 = UDRO USB DMA Request Out. This bit is set and cleared by hardware by the USB cell. This bit is set when the USB OUT endpoint assigned to the MSCI is empty and waiting for data 0: No request 1: USB DMA request for OUT endpoint Bit 4 = UDRI USB DMA Request In. This bit is set and cleared by hardware by the USB cell. This bit is set when the MSCI dedicated USB IN endpoint is full and waiting to be flushed: 0: No request 1: USB DMA request for IN endpoint Bit 3 = LWR Last Word Read. This bit is set by hardware when the last word of the last packet of message has been read in the FIFO and cleared by software by writing '1'. 0: No message / message not buffered 1: Message buffered
Bit 2 = CP Communication in Progress. This bit is set and cleared by hardware when a communication is in progress. Because of internal VCI interface pipelining, the user must check that the CP bit is '0' before turning off the VCI interface. For write operations in burst mode, CP is set after the first word has been written in the FIFO. 0: No Communication 1: Communication in Progress Bit 1 = FF FIFO Full. This bit is set and cleared by hardware when the FIFO is full. 0: FIFO not full 1: FIFO full Bit 0 = FE FIFO Empty. This bit is set and cleared by hardware when the FIFO is empty. 0: FIFO not empty 1: FIFO empty
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MSCI VCI INTERFACE (Cont'd) VCI TARGET ADDRESS REGISTER (VTAR) Read / Write Reset Value: 0000 0000 0000 0000 (0000h)
15 8 7 AD5 AD4 AD3 AD2 AD1 0 AD0
Bit 15:6 = Reserved.
Bit 5:0 = TA[5:0] Target Address. Target address. Can be read or written by software. It can only be written when no communication is active.
VCI FIFO DATA REGISTER (VFDR) Read / Write Reset Value: 0000 0000 0000 0000 (0000h)
15 D15 D14 D13 D12 D11 D10 D9 8 D8 7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 15:0 = FD[15:0] FIFO Data. FIFO Data. Can be read or written by hardware and software.
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MSCI VCI INTERFACE (Cont'd) 16.4.2 MSCI VCI Interface software example 16.4.2.1 Burst mode / scalar mode The program below gives an example of MSCI control flow between VCI and the data RAM in burst mode:
CLR DP1 LDl VTAR, #$20 LDl VCR, #$03 AUTOINC CALL RDBK CPBS VSR, #3 JPNCond LOOPR CLR CONF_W VCR ; ; ; ; Clear data pointer Target : USB output FIFO VCI On in burst mode Set Autoinc mode
CONF_R
LOOPR
; Read 8-word block ; Last block ? ; If not loop ; Turn off the VCI ; ; ; ; ; ; ; ; ; ; ; ; ; VFDR VFDR VFDR VFDR VFDR VFDR VFDR VFDR Target : USB input FIFO VCI On in burst mode Clear Data Pointer Set Autoinc mode Wait On Set mode Wait for FIFO empty Write 8-word block DP1 = $100 ? If not, continue Wait on Reset mode Wait for the end of communication Turn off the VCI interface End of routine
LDl VTAR, #$21 LDl VCR, #$03 CLR DP1 AUTOINC WOSet WBS CALL CPBS JPNCond WORst WBS CLR STOP VSR, #0 WRBK DP1, #8 LOOPW
LOOPW
VSR, #2 VCR
RDBK
LD LD LD LD LD LD LD LD RET LD LD LD LD LD LD LD LD RET
[DP1]+, [DP1]+, [DP1]+, [DP1]+, [DP1]+, [DP1]+, [DP1]+, [DP1]+,
WRBK
VFDR, VFDR, VFDR, VFDR, VFDR, VFDR, VFDR, VFDR,
[DP1]+ [DP1]+ [DP1]+ [DP1]+ [DP1]+ [DP1]+ [DP1]+ [DP1]+
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MSCI VCI INTERFACE (Cont'd) 16.4.2.2 Burst mode / vectored mode The program below gives an example of MSCI control flow between VCI and another interface with a FIFO called PFR through the vectored bus in burst mode: Transfer from VCI to parallel interface in vectored mode
INIT_R LDl LDl LDh LDl LDh LDl LDl WOSet WBS LDv CPBS JPNCond WBS CLR PCR2,#$29 PCR1,#$2A PCR1,#$00 PNDR,#$00 PNDR,#$02 VTAR, #$20 VCR, #$03 PSR, #0 PFDR,VFDR VSR, #3 LOOPR PSR, #2 VCR ; init for parallel itf ; INPUT 20 MHz for NAND ; 8-bit lsb input ; 512 bytes to send ; ; ; ; ; ; ; Target : USB output FIFO VCI On in burst mode Wait On Set mode Wait parallel itf fifo empty Read 8-word block Last block ? If not loop
CONF_R
LOOPR
; Wait for the end of communication ; Turn off the VCI
Transfer from parallel interface to VCI in vectored mode
INIT_W LDl LDl LDh LDl LDh LDl LDl WOSet WBS LDv CPBS JPNCond WORst WBS CLR PCR2,#$28 PCR1,#$b2 PCR1,#$02 PNDR,#$00 PNDR,#$02 VTAR, #$21 VCR, #$03 ; init for parallel itf ; 15 MHz for NAND output ; RE and 16-bit ; 512 bytes to read ; Target : USB input FIFO ; VCI On in burst mode ; Wait On Set mode ; ; ; ; Wait for VCI itf FIFO empty Write 8-word block Last block? If not, continue
CONF_W
LOOPW
VSR, #0 VFDR, PFDR PSR, #3 LOOPW
VSR, #2 VCR
; Wait on Reset mode ; Wait for the end of communication ; Turn off the VCI interface
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MSCI VCI INTERFACE (Cont'd) 16.5 USB register addressing The MSCI VCI interface enables the access to the USB registers and FIFO. As described in the MSCI VCI interface the USB registers can be accessed either in 8-bit or 16-bit word. Due to the fact that the USB is designed using a little-endian structure and ST7 a big endian structure the USB address for the MSCI is different from the one described in USB chapter (ST7 addressing). The USB register mapping is described in table 39 for a access in 8-bit mode and table 40 for an access in 16-bit mode (to an even address) Table 33 describes the byte accessed when odd address is accessed in 16-bit mode. Table 33. Byte accessed in 16-bit mode
Address 0 1 2 Byte accessed 1 2 3 0 1 2
Important note: Before accessing an indexed register (endpoint status and control registers, address 10h to 18h) the endpoint number to be accessed have to be written in EP bits of VCR register (bit 9:8). The default endpoint addressed (reset value) is endpoint 2. Due to the fact that the MSCI is a 16-bit core it is naturally recommended to access the buffer in 16bit mode (normal or burst mode).
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Table 34. USB Register Map with Reset Values seen from MSCI through VCI interface (8-bit access)
Address (Hex.)
00h
Register Name
FADDR Reset Value PWRR Reset Value ITINR Reset Value ITOUTR Reset Value ITINER Reset Value ITOUTER Reset Value ITUSBR Reset Value ITUSBER Reset Value FRNBRL Reset Value FRNBRM Reset Value
7
UPD 0 0
6
FAD6 0 SCON 0 0
5
FAD5 0 HSE 1 0
4
FAD4 0 HSM 0 0
3
FAD3 0 RST 0 0
2
FAD2 0 RSM 0 EP2I 0 EP2O 0 EP2IE 1 EP2OE 1 RST 0 RSTE 1 FN2 0 FN10 0
1
FAD1 0 SUSM 0 EP1I 0 EP1O 0 EP1IE 1 EP1OE 1 RSM 0 RSME 1 FN1 0 FN9 0
0
FAD0 0 ESUSM 0 EP0 0 0 EP0E 1 0 SUSP 0 SUSPE 0 FN0 0 FN8 0
01h
02h
0
04h
0
0
0
0
0
06h
0
0
0
0
0
08h
0
0
0
0
0 SOF 0 SOFE 0 FN3 0 0
0Ah
0
0
0
0
0Bh
0 FN7 0 0
0 FN6 0 0
0 FN5 0 0
0 FN4 0 0
0Ch
0Dh
0Eh RESERVED 0Fh INMAXPRL Reset Value INMAXPRM Reset Value INCSRL (CSR0) IND=0 Reset Value INCSRL IND=1 or 2 Reset Value INCSRM IND=0 Reset Value INCSRM IND=1 or 2 Reset Value OUTMAXPRL Reset Value IMP7 0 0 SSE 0 0 IMP6 0 0 SOPR 0 CDT 0 0 IMP5 0 0 SDST 0 STST 0 0 IMP4 0 0 SE 0 SDST 0 0 DMAE 0 OMP4 0 IMP3 0 0 DE 0 FLFI 0 0 FDT 0 OMP3 0 IMP2 0 IMP10 0 STST 0 UNDR 0 0 IMP1 0 IMP9 0 IPR 0 FINE 0 0 IMP0 0 IMP8 0 OPR 0 IPR
10h
11h
12h
0 ASET 0 OMP7 0
0
13h
0 OMP6 0
0 OMP5 0
0 OMP2 0
0 OMP1 0
0 OMP0 0
14h
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Address (Hex.)
15h
Register Name
OUTMAXPRM Reset Value OUTCSRL Reset Value OUTCSRM Reset Value OUTCNTRL Reset Value OUTCNTRM Reset Value
7
6
5
4
3
2
OMP10 0 0
1
OMP9 0 FIFU 0 0 OC1 0 OC9 0
0
OMP8 0 OPR 0 0 OC0 0 OC8 0
0 CDT 0 ACLR 0 OC7 0 0
0 STST 0 0 OC6 0 0
0 SDST 0 DMAE 0 OC5 0 0
0 FLFI 0 DNY 0 OC4 0 OC12 0
0
16h
0 DMAM 0 OC3 0 OC11 0
17h
0 OC2 0 OC10 0
18h
19h
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Table 35. USB Register Map seen from MSCI through VCI interface (16-bit access)
Addr. (Hex.)
00h
Register Name
PWRR / FADDR ITINR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
SCO N 0
HSE
HSM
RST
RSM
SUS M 0
ESUSM 0
UPD
FAD 6 0
FAD 5 0
FAD 4 0
FAD 3 0
FAD 2 EP2I EP2 O EP2I E EP2 OE RST
FAD 1 EP1I EP1 O EP1I E EP1 OE RSM
FAD 0 EP0
02h
0
0
0
0
0
0
04h
ITOUTR
0
0
0
0
0
0
0
0
0
0
0
0
0
0 EP0 E 0 SUS P FN0
06h
ITINER
0
0
0
0
0
0
0
0
0
0
0
0
0
08h
ITOUTER ITUSBER / ITUSBR FRNBR
0
0
0
0
0 SOF E 0
0 RST E 0
0 RSM E FN10
0 SUS PE FN8
0
0
0
0
0
0Ah
0
0
0
0
0
0
0
0
SOF
0Ch
0
0
0
0
FN7
FN6
FN5
FN4
FN3
FN2
FN1
0Eh
RESERVED IMP1 IMP9 IMP8 IMP7 IMP6 IMP5 IMP4 IMP3 IMP2 IMP1 IMP0 0 SSE ASE T 0 ACL R 0 DMA E 0 SOP R CDT SDS T STS T SE SDS T DE STS T UND R IPR OPR
10h
INMAXPR INCSR (CSR0) IND=0 INCSR IND=1 or 2
0
0
0
0
0
12h
0
0
FDT
0
0
0
0
FLFI
FINE
IPR OMP 0 OPR
14h
OUTMAXPR OUTCSR
0
0 DMA E 0
0 DMA M OC1 1 D11
OMP OMP 10 9 0 OC1 0 D10 0
OMP OMP 8 7 0 CDT
OMP OMP 6 5 STS T OC6 SDS T OC5
OMP OMP 4 3 FLFI 0
OMP OMP 2 1 0 FIFU
16h
0
DNY OC1 2 D12
18h
OUTCNTR Endpoint 0 OUT FIFO (Read) Endpoint 0 IN FIFO (Write) Endpoint 1 OUT FIFO (Read) Endpoint 1 IN FIFO (Write)
0
OC9
OC8
OC7
OC4
OC3
OC2
OC1
OC0
D15
D14
D13
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
20h
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
22h
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
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Addr. (Hex.)
Register Name
Endpoint 2 OUT FIFO (Read) Endpoint 2 IN FIFO (Write)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
24h
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
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17 MSCI PARALLEL INTERFACE
17.1 INTRODUCTION The MSCI Parallel Interface is a hardware block controlled by the MSCI core. It provides fast parallel communication in master mode with the following capabilities: 8 or 16-bit data width. 8 control lines to output the configurable control signal. High speed continuous data flow can be obtained with internal double buffering. 22-bit ECC Error Code correction generator for 1 bit correction in 256 byte packet. Hardware Reed Solomon encoder and decoder correcting 4 bytes in a 512-byte packet. 17.2 FUNCTIONAL DESCRIPTION The parallel interface can be used in input or output. Three data width configurations can be used: 8-bit data on first half of the 16-bit data port 8-bit data on second half of the 16-bit data port Figure 55. MSCI parallel Interface Block Diagram
MSCIcoreclk
16-bit data. In output mode the parallel interface automatically sends data on data I/O ports (8-bit or 16-bit) and generates Write Enable or clock signals on dedicated I/Os. Data is output at beginning of cycle. In input mode the parallel interface automatically reads data from data I/O ports (8-bit or 16-bit) and generates Read Enable or clock signals on dedicated I/Os. Data can be sampled either at the end of each cycle or on the edge of the control signal. The shape of the control signals, the clock frequency, the control signals output ports can be controlled with dedicated configuration registers. note: All the control signals are generated by only one generator and have the same shape. Two Error Code Corrections algorithms are available to ensure data reliability. One ECC generator compliant with Smart Media Card specification (1bit correction in 256-byte packets) and one Reed Solomon algorithm (4-byte correction in 512-byte packets) with full hardware encoding and decoding.
PARALLEL INTERFACE
Read/Write Registers Read Only Flag Registers FIFO byte swap FIFO 8*16-bit copy buffer status Parallel Interface State Machine
MSCIperiphclk
MSCI CORE
MSCI Bus
128-bit
16-bit
Clock Prescaler
Vectored Bus
direct 128-bit
VCI INTERFACE
Communication buffers buffer0 buffer1 8*16-bit 8*16-bit
.
PORT1 INPUT
sampling
ECC generator RS encoder
Control signal generator RSEclk RSDclk
REED SOLOMON 512 bytes RAM
RS decoder
triggered inputs from pins
alternate output alternate enable MSCI I/O Port 1
alternate enable alternate output MSCI I/O Port 2
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MSCI PARALLEL INTERFACE (Cont'd) 17.2.1 FIFO management 17.2.1.1 Input mode In input mode the FIFO is filled by the parallel interface and emptied by MSCI software when all FIFO words are read by the MSCI core. When the FIFO is empty and a communication buffer is full, the buffer is copied into the FIFO. The FF flag is set. The MSCI software can read all the words received by the FIFO by reading the PFDR register. Each time a read access is performed, the words are shifted out of the FIFO. First read access returns the first word received, second read access returns the second word received and so on... When the MSCI software reads the 8th word, the FIFO status is set to "empty". If more data is to be read, then the FIFO will be filled again as soon as the communication buffer is ready. (buffer0/ buffer1 selection is round robin). The position of the bytes in the word can be reversed when reading the FIFO if the FIFO Swap Byte bit is set (bit 1 of the PCR2 register). If a read operation is performed on the PFDR when the parallel communication interface is conFigure 56. FIFO management in input mode
figured in input mode and when the FIFO is not full, the MSCI core is frozen until data is available from the FIFO (this also works with LDV instruction). If the number of words to receive is not a multiple of 8 (size of the FIFO), the FIFO will be set to full when the last words of the communication are ready in the communication buffer. The program can read all the FIFO words to clear the FIFO (FIFO status reset to empty) or read only the necessary words and reset the FIFO status by writing '1' in the bit 13 of the PCR2 register. The FIFO status must not be cleared when communication is on going, the MSCI program must first check that the EOC flag is set (bit 2 of the PSR register). Note: The last data received (8-bit or 16-bit) is also saved internally and used by the ECC generator when the parallel interface is configured in input mode (or by the Reed Solomon encoder/decoder when enabled)
MSCI bus
FSB
byte swap
16 bit
16-bit Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7 FIFO 128bit Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7 COM. BUFFER(0 or 1) Data from PADS
last data received
for redundancy generators/decoder
128-bit byte swap 128-bit in each word
vectored bus
FSB
128-bit
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MSCI PARALLEL INTERFACE (Cont'd) 17.2.1.2 Output mode In output mode, the FIFO is filled by the software and emptied by the parallel interface: each time a write access is performed by the MSCI software, the words are stored in the FIFO at the next location. When the MSCI software writes the 8th word, the FIFO status is set to "full". When the FIFO is full and one of the double communication buffer is empty, the FIFO is copied to the free buffer. The FE flag is set after this copy is done. If the communication is not over the FIFO can be filled again by the software and so on... The flag "Last Byte into FIFO" (bit 3 of the PSR register) is set when the last expected word is written in the FIFO. The position of the bytes in the word can be reversed when writing into the FIFO if the FIFO Swap Byte bit is set (bit 1 of the PCR2 register). If a write operation is performed on the PFDR when the parallel communication interface is configured in output mode and when the FIFO is full, the word is not stored in the FIFO. Figure 57. FIFO management in output mode
vectored bus byte swap 128bit in each word 128bit 128bit FIFO
A full FIFO write with the LDV instruction must not be performed if the FIFO is not empty. The program must wait for FIFO empty before writing the FIFO with a LDV instruction otherwise data may be lost. If the number of words to send is not a multiple of 8 (size of the FIFO), the FIFO will be copied in the communication buffer as soon as a buffer is empty and the last byte is written in the FIFO. The FIFO flag full is not set but if other words are written in the FIFO while the flag "Last Byte into FIFO" is set, the words are not stored in the FIFO. No other word can be written in the FIFO until a new start pulse is generated by writing 1 in the bit 15 of the PCR1 register. (the Last Byte into FIFO fag is cleared by the start pulse). In output mode, each data is output at the beginning of the cycle and stays up till the end of one cycle. Note: In output mode the ECC generator (and the Reed Solomon encoder/decoder if enabled) receive the value sent to I/Os.
COM. BUFFER(0 or 1) Word 0 Word 1 Word 2 128bit Word 3 Word 4 Word 5 Word 6 Word 7 for redundancy generators/decoder Data to MSCI I/O controller
FSB
Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
16-bit
16 bit
byte swap
16-bit
MSCI bus
FSB
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MSCI PARALLEL INTERFACE (Cont'd) 17.3 CONFIGURING THE CONTROL LINES Eight lines are available to provide automatic control signals output toward external communication devices. Only one control signal generator is used to create one control signal that can be output on eight dedicated I/Os. One output enable signal is available for each output (bits 4 to 11 of the PCR2 register). If an enable bit is set, the corresponding I/O is forced to output mode and controlled by the control signal generator. If the enable signal is reset, the corresponding I/O can be controlled by the MSCI I/O registers. 17.3.1 Control Signal Enable bits When enabling some control signals by setting the corresponding CSE bits of the PCR2 register, unexpected pulse can be observed on I/O when CLDV value if the port was previously in input mode or if the port level was not the value chosen for CLDV. To avoid an unexpected pulse on the control I/Os when switching from MSCI I/O controller to parallel interface control, the following MSCI software sequences must be used: If control I/Os were previously in input mode: a) Configure CLDV bit of the PCR2 register with all control lines disabled. b) Load the MSCI I/O Controller DRO bits corresponding to the control I/O used with the CLDV value. c) Select output mode with MSCI I/O controller for the control line I/O by setting the corresponding bits of the DDR register. d) Set the control signal enable bits in the PCR2 register. If control I/Os were already configured in output mode by MCI I/O logic: a) Configure CLDV bit of the PCR2 register with all control lines disabled. b) Load the MSCI I/O controller DRO bits corresponding to the control I/O used with the CLDV value. c) Set the control signals enable bits in the PCR2 register. 17.3.2 Control Signal Parameters When a communication is started, a pulse is output for each data sent to (or read from) the data I/ Os. The shape of this pulse can be configured with the PCR1 and PCR2 registers. The parameters described in this chapter must be configured to obtain the desired control signal. 17.3.2.1 Control Line Default Value (CLDV) CLDV (bit 0 in the PCR2 register) The Control Line Default Value is the value that is output on enabled control I/Os when communication is not running. Figure 58. Effect of CLDV Parameter
commnunication not started
communication on going
commnunication terminated
CLDV=1
CLDV=0
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MSCI PARALLEL INTERFACE (Cont'd) 17.3.2.2 Frequency Prescaler (F) F[2:0] (bits 6:4 of the PCR1 register) Frequency prescaler is used to select the duration of the control signal pulse (and the frequency of the data output/input). The output frequency Fo is:
60 Fo = ----------------- MHz (F + 1)
The period of the control signal is (F+1) times higher than the base period of 60 MHz Note: the value F[2:0]=000 is not allowed. Maximum frequency is obtained for F=001 => 30MHz 17.3.2.3 Effect of F Parameter
(example with fixed CSS=001)
cycle of the pulse signal. They represent the position of the edge relative to the beginning of the cycle. If the value selected is 001 the control signal edge (rising or falling) will occur 1 period of the 60MHz base frequency after the beginning of the clock cycle. If the value selected is 010, the control signal edge (rising or falling) will occur 2 periods of the base frequency after the beginning of the clock cycle and so on... For this reason, this value must be lower than the value selected for the frequency selection or equal to this value otherwise, the control signal will remain stable during the whole clock cycle. For the same reason, this value must also be greater than zero. Figure 59. Effect of CSS Parameter
(example with fixed F=111)
F=001 CSS=001 F=010 CSS=010 F=011 CSS=011 F=111 CSS=111 60MHz base period 60MHz base period
17.3.2.4 Control Signal Shape (CSS) CSS[2:0] (bits 2:0 of the PCR1 register) The Control Signal Shape bits are used to select the duty
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MSCI PARALLEL INTERFACE (Cont'd) 17.3.2.5 Clock Polarity (CP) CP (bit 3 of the PCR1 register) Clock Polarity. This bit is used to select whether the pulse will be a rising or a falling edge (0=falling edge, 1=rising edge). If CP=0 the control signal value will be 1 at the beginning of the cycle and will fall to 0 during the cycle according to the value chosen for CSS parameter. If CP=1 the control signal value will be 0 at the beginning of the cycle and will rise to 1 during the cycle according to the value chosen for CSS parameter Figure 60. Effect of CP Parameter
(example with fixed CSS=010 F=011)
pulse1
pulse2
pulse3 pulse4
CP=0 (falling edge) CP=1 (rising edge)
Important note: The timings shown in the figures are those obtained while communication is continuous (no parallel interface double buffer underrun or overrun). However this can be performed only if the data transfer to/from the FIFO is faster than the communication data transfer rate: - In output mode, if the FIFO can't be filled as fast as the double buffer is sent to I/Os, the communication is stopped each time the double buffer is empty. The control signal is stretched until one buffer is full (no additional pulse generated). - In input mode, if the FIFO is not read by MSCI software as fast as the data is read from I/Os, the communication is stopped each time the double buffer is full. The control is stretched to inactive state until one buffer is empty. - If "read on edge" mode is selected the data sampling position will not be modified. - In "read at end of cycle" mode, the sampling will be performed at the end of the stretched cycle (external data is assumed to be maintained until the end of the stretched cycle)
60MHz base period
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MSCI PARALLEL INTERFACE (Cont'd) 17.4 MSCI PARALLEL INTERFACE CONFIGURATION EXAMPLES 17.4.1 Examples for output mode Once the parallel interface is configured and started, the communication begins as soon as one communication buffer is full. If the double buffer is filled by the MSCI software (through the FIFO) faster than the data is sent to the I/Os, the communication will be continuous during the complete packet. If the buffer becomes empty during a communication, inactive states will be inserted to wait until the buffer is ready. During these inactive states, the data port is not driven by the parallel interface, the control lines are frozen at the CLDV level (Control Lines Default Value). In output mode, data is always output at the beginning of the control signal cycle whatever the control signal is. The control signal must be configured in order to match targeted device protocol. The Control Line Default Value (CLDV) parameter is specific and must be configured before others control signals parameter and before enabling any Control Signal output with the CSE bits of the PCR2 register.
Figure 61. Examples: output mode with F=010; CSS=010
Frequency=20MHz; Duty Cycle=33% 60MHz base period control signal edge 2 periods after the beginning of the control cycle waiting for Buffer full again
Control signal port
CLDV=1 CP=1 CLDV=0 CP=1 CLDV=1 CP=0 CLDV=0 CP=0
DATA ports
Data output
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
data ports controlled by MSCI I/O Controller
Data ports selected (depending on the mode) controlled by parallel interface
data ports controlled by MSCI I/O Controlle
Note: In output mode, short spikes can be generated on data ports before data is stable (shorter. . than the data output delay). Only the Control line signals are guaranteed to be spike free signals (mandatory for synchronous communication).
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MSCI PARALLEL INTERFACE (Cont'd) 17.4.2 Examples for input mode Once the parallel interface configured and started, the communication begins. If the double buffer is read by the MSCI software (through the FIFO) faster than the data is received from the I/Os, the communication will be continuous during the complete packet. If the two buffers become full during a communication, inactive states will be inserted to
wait until the buffer is ready. During these inactive states, the control lines are frozen at the CLDV (Control Lines Default Value) level. The data ports used are not forced to input mode by the parallel interface. They must be configured in input mode by the MSCI I/O controller (and by the ST7 I/O Controller) to let an external device drive them.
Figure 62. Examples: input mode with F=010; CSS=010; CP=1; CLDV=1
CTRL signal port
CLDV=1 CP=1
DATA ports
sync device data output
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
async device data output
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
If the device is synchronous and outputs data after the falling edge, the ROE can be reset to sample at the end of the control signal cycle if setup time can be guaranteed. If setup time can not be guaranteed, then the ROE bit must be set (data output time of the external device must be shorter than the low level time on control line) If the device is asynchronous and data is output only when control signal is low, the ROE bit must be set to sample data on the rising edge of the control signal. (data output time of the external device must be shorter than the low level time on control line)
data sampling if ROE=1 data sampling if ROE=0
Note: If CP=0 configuration is selected (falling edge generated) only the control signal generation will be modified. This means that data will be sampled on the falling edge of the control signal if ROE=1 or at the end of the control signal if ROE=0.
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MSCI PARALLEL INTERFACE (Cont'd) 17.5 CASE OF NON CONTINUOUS DATA FLOW 17.5.1 Double buffer underflow in output mode If the MSCI software is not able to send data fast enough to the FIFO while the MSCI parallel interface still has to send data, the communication stops until FIFO is filled again and copied into the communication buffer. The control signal is forced to the CLDV state and no data is driven on the port by the parallel interface (data I/O state is controlled by the MSCI I/O Controller when communication is frozen). see Figure 63 17.5.2 Double buffer overflow in input mode If the MSCI software is not able to read data fast enough from the FIFO while the MSCI parallel interface still has to store data, the communication stops until a communication buffer is free again. If the option ROE=1 is selected, the control signal is forced to the CLDV state and no data is driven on the port by the parallel interface (data I/O state depends on the MSCI I/O Controller). If the option ROE=0, the last value of the control signal is kept on the port until a buffer is available. (last data is read at the end of the stretched cycle) In both cases, no additional pulse is generated. see Figure 64
Figure 63. Example: output mode with CP=1 CLDV=1 F=010; CSS=010
double buffer not empty double buffer empty double buffer not empty
Control Signal
Data output
D12
D13
D14
D15
depends on MSCI I/O Controller register values
D16
D17
D18
D19
data port driven by parallel interface
data ports controlled by MSCI I/O Controller
data port driven by parallel interface
port still driven by parallel interface for one 60 MHz period
Figure 64. Examples: input mode with CP=1 CLDV=0 F=010; CSS=010
double buffer not full Control Signal ROE=0 double buffer full double buffer not full
ROE=1
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MSCI PARALLEL INTERFACE (Cont'd) 17.6 ECC GENERATOR The ECC generator is a hardware system that computes Error Code Correction parity bits from data sent or received by the parallel interface. It is compliant with the Smart Media Card specification. It allows correction of one bit in each 256-byte data packet. It is designed to work with 512-byte packets: two ECC codes are stored in internal registers and can be read by the MSCI core after the 512-byte packet has been sent or received by the parallel interface. Each Generated code is made of 16 line parity bits and 6 column parity bits. This 22bit ECC is generated every 256 bytes of data. If the parallel interface is used in 16-bit data mode, the data word is split into two bytes that are sent to the ECC generator. The order of the bytes in the word for the ECC generator can be selected with the bit 2 of the Figure 65. ECC generator implementation
COM. BUFFER (0 or 1) Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
previous data word received from I/Os
Input or Output mode ECC swap bytes ECP2 register word/byte conversion ECC generator ECP1 register
PCR2 register (ECC Swap Bytes). For each 512byte packet, two ECC results are automatically stored by the ECC generator without interrupting the communication. The ECC generated for the first 256 bytes is stored in the ELP1 and ECP1 registers, the ECC generated for the next 256 bytes is stored in the ELP2 and ECP2 registers. If more than 2*256 bytes are sent/received, only the two first ECCs are stored. Two flags are available in the PSR register to indicate whether ECC1 and ECC2 are available for reading or not. The ECC generator and the ECC line and column parity registers are reset when a new start is performed on the parallel interface.
ECC1 stored
ELP1 register
ECC2 stored
ELP2 register
Status flags
ECC1 ready ECC2 ready
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MSCI PARALLEL INTERFACE (Cont'd) 17.7 REED SOLOMON ENCODER The Reed Solomon encoder is a hardware system that computes error code correction parity symbols from data sent (or received) by the parallel interface. It allows the correction of 4 bytes in each 512-byte packet. The RS encoder works with 10 bit symbols. The 2 most significant bits of the RS encoder input are forced to 0 by hardware. The generated code is made of eight 10-bit symbols that can be read as five 16-bit words by the MSCI core after the "parity symbols ready" flag is set. If the parallel interface is used in 16-bit data mode, the data word is split into two bytes that are sent to the ECC generator. The order of the bytes in the word for the ECC generator can be selected with bit 2 of the PCR2 register (ECC Swap Bytes) The redundant code in the output FIFO is replaced each time a new set of parity symbols is available. The output FIFO status can not be reset by MSCI software, all five 16-bit words must be read in order to make the FIFO point to the first word again. Reading this register when the FIFO is not ready does NOT freeze the MSCI CPU.
Figure 66. Reed Solomon encoder implementation (When RS encoder enable = 1)
COM. BUFFER (0 or 1) Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
previous data word received from I/Os Status flags
Input or Output mode ECC swap bytes word/byte conversion RS encoder 8*10bit Output FIFO (5*16-bit)
MSCI 16-bit BUS
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MSCI PARALLEL INTERFACE (Cont'd) 17.8 REED SOLOMON DECODER The Reed Solomon decoder is a hardware system that can detect and correct 4 erroneous bytes in a 512-byte data packet received (or sent) by the parallel interface. It must receive packets made of 520 10-bit symbols (512 data symbols followed by 8 parity symbols). See Figure 67 The data symbols are provided to the decoder by the parallel interface when the decoder is enabled. They are converted to 10 bit by adding 2 most significant bits and forcing them to 0. The parity symbols must be sent to the decoder through a dedicated input FIFO. This FIFO makes the conversion from 16-bit words to 10-bit words for the parity symbols. After receiving a complete packet of 520 symbols, the Reed Solomon decoder automatically starts its algorithm. After a few cycles it is able to indicate whether the packet is corrupted with the "errors" and "errors_valid" flags. If the packet contains errors, the correction algorithm is automatically started. After approximately 20 MSCI cycles (depends on the error) the Reed Solomon is ready to output 512-byte corrected data packed. Data output of the decoder can be read through a dedicated output FIFO. See Figure 68 The Input FIFO can be filled at any time by the MSCI core. When the RS decoder has received all the data bytes, the MSCI program must send the redundant symbols to the decoder. To do this the MSCI software must write 1 in the "Feed Decoder" bit of the RSCSR register. This sends the content of the input FIFO in 10-bit format to the decoder. The redundancy words must be sent in the same order and with the same byte ordering as they were read from the encoder output! The output FIFO is automatically filled by the decoder when the errors are corrected (this only happens if an error was detected). The MSCI software can recover the 512-byte data packet from this output FIFO by series of eight 16-bit words. Note: the same register is used to access input FIFO and output FIFO of the RS decoder. Writing into this register store data in the input FIFO, reading this register returns data from the output FIFO.
Figure 67. Reed Solomon 520-symbol frame. 520 symbols
2 MSB of data symbols forced to 0
512 data bytes
8 parity symbols
10 bits
Figure 68. Reed Solomon decoder implementation (When RS decoder enable = 1)
COM. BUFFER (0 or 1) Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
previous data word received from I/Os 512byte RS decoder RAM
Input or Output mode ECC swap bytes word/byte conversion RS decoder Decoder output FIFO (8*16-bit)
Status flags
Decoder input FIFO (5*16-bit)
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MSCI PARALLEL INTERFACE (Cont'd) Figure 69. Typical decoding flow with Reed Solomon decoder MSCI SOFTWARE read redundant codes with parallel interface and store into data memory RS decoder disabled HARDWARE RS DECODER
decoder not enabled
enable the decoder
decoder ready to receive data symbols
read 512 bytes of data with parallel interface
decoder receiving data symbols
copy parity data for the block in RS input FIFO and feed decoder
decoder receiving parity symbols
wait for error_ready=1
Check if packet contains erroneous data
NO errors=1? YES correction algorithm running. wait for output FIFO full (not mandatory) errors=1? YES
NO
data corrected and ready
copy FIFO into target
sending data symbols to FIFO until last symbol is sent
NO last word read? YES
Flag "DEOC" <= 1 Uncorrectable flag ready
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MSCI PARALLEL INTERFACE (Cont'd) 17.9 MSCI SOFTWARE EXAMPLES 17.9.1 Loop for data send This loop can be used even if the number of bytes to send is not multiple of 16 (size of the FIFO). The extra words written in the FIFO are ignored.
;-------------------------------; CONFIGURE SEND ;-------------------------------LDl PCR2,#$19 ; LDl PCR1,#$AA ; 20 MHz for NAND LDh PCR1,#$01 ; RE and 8-bit on msb LDl PNDR,#$00 LDh PNDR,#$02 ; 512 bytes to send BSET PCR1,#15 ; start // transfer CLR DP0 ; CLEAR DP0 pointer CALL SEND_DATA STOP SEND_DATA WOSet LOOP_SEND WBS PSR,#0 LD PFDR,[DP0]+ LD PFDR,[DP0]+ LD PFDR,[DP0]+ LD PFDR,[DP0]+ LD PFDR,[DP0]+ LD PFDR,[DP0]+ LD PFDR,[DP0]+ LD PFDR,[DP0]+ CPBS PSR,#3 JPNCond LOOP_SEND WBS PSR,#2 RET
;wait for FIFO empty ;.Fill FIFO ;..Fill FIFO ;...Fill FIFO ;....Fill FIFO ;.....Fill FIFO ;......Fill FIFO ;.......Fill FIFO ;........Fill FIFO ;last bytes stored in FIFO? ;if no loop ;else wait untill End Of Transmit... ;and return to main program
Note: FIFO can also be filled using vectorial mode. Please refer to VCI interface software example section.
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MSCI PARALLEL INTERFACE (Cont'd) 17.9.2 Loop for data read This loop can be used only if the number of bytes to receive is not multiple of 16 (size of the FIFO) otherwise, extra bytes would be read that do not belong to the communication frame. In input mode, the FIFO is set to full when the last bytes are received.
;-------------------------------; CONFIGURE READ ;-------------------------------LDl PCR2,#$29 ; CS1 LDl PCR1,#$2A ; INPUT LDh PCR1,#$01 ; 8-bit msb input LDl PNDR,#$00 LDh PNDR,#$02 ; 512 bytes to read BSET PCR1,#15 ; start // transfer CLR DP0 ; CLEAR DP0 pointer CALL READ_DATA STOP READ_DATA WOSet LOOP_READ ;WBS PSR,#1 LD [DP0]+,PFDR LD [DP0]+,PFDR LD [DP0]+,PFDR LD [DP0]+,PFDR LD [DP0]+,PFDR LD [DP0]+,PFDR LD [DP0]+,PFDR LD [DP0]+,PFDR CPBS PSR,#3 JPNCond LOOP_READ WBS PSR,#2 RET
;wait for FIFO full (not mandatory because if fifo ;is empty MSCI core is freezed ) ;........Read FIFO ;.......Read FIFO ;......Read FIFO ;.....Read FIFO ;....Read FIFO ;...Read FIFO ;..Read FIFO ;.Read FIFO ;last bytes read from FIFO ??? ;if no loop ;else wait untill rnd Of reception... ;and return to main program
Note: FIFO can also be transferred into VCI FIFO using vectored mode. Please refer to VCI interface software example section.
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MSCI PARALLEL INTERFACE (Cont'd) 17.10 REGISTER DESCRIPTION PARALLEL INTERFACE NUMBER OF DATA REGISTER (PNDR) Read / Write Reset Value: 0000 0000 0000 0000 (0000h
15 N9 8 N8 7 N7 N6 N5 N4 N3 N2 N1 0 N0
Bit 15:10 = Reserved Bit 9:0 = N[9:0] Number of Data Register. Number of bytes to send in output mode or to read in input mode. Must be strictly positive (value 00h is not allowed). In 16-bit mode, this number must be even. If the number of bytes to send/receive is odd in 16-bit mode, the last incomplete word is not sent/read. PARALLEL INTERFACE FIFO DATA REGISTER (PFDR) Read/Write Reset Value: 0000 0000 0000 0000 (0000h)
15 D15 D14 D13 D12 D11 D10 D9 8 D8 7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 15:0 = D[15:0] FIFO Data. When the parallel interface is configured in output mode (PCR1[7]=1), writing to this register adds one word to the FIFO. Writing into the FIFO when it is already full has no effect. Write access in the PFDR register can only be performed in 16-bit mode. Immediate 8bit write through LDL or LDM or BSET/BRES must not be used on this register. When the parallel interface is configured in input mode PCR1[7]=0, reading this register returns one word from the FIFO. If FIFO is empty when reading this register, the parallel interface sends a freeze signal to the MSCI core until the FIFO is filled.
Refer to the FIFO management Section 17.2.1 for more information.
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MSCI PARALLEL INTERFACE (Cont'd) PARALLEL INTERFACE CONFIGURATION REGISTER 1 (PCR1) Read / Write Reset Value: 0000 0000 0111 1111 (007Fh)
15 START DM1 8 DM0 7 DIR F2 F1 F0 CP CSS2 CSS1 0 CSS0
Bit 15 = START Start communication.(write only) This bit is set by software and is always read as 0. Setting in this bit generates a start pulse that initiates the data transfer. In input mode communication starts immediately (FIFO must be empty). In output mode communication starts as soon as the FIFO is full and copied into the buffer. Bit 14:10 = Reserved. Bit 9:8 = DM[1:0] Data Mode. These bits are set and cleared by software. When 8-bit output mode is used, data bytes are sent to port P1[7:0] or P1[15:8] depending on whether the LSB or MSB mode is selected. In 16bit mode, data is sent to P1[15:0]. When 8-bit mode is used, the most significant byte is sent or read first. The FSB bit in the PCR2 register can be used to reverse byte order when writing into the FIFO or reading from the FIFO (equivalent to sending or reading least significant byte first). 00: 8-bit mode on LSB only 01: 8-bit mode on MSB only 10: 16-bit mode. Bit 7 = DIR Direction. This bit is set and cleared by software. In output mode the data ports used are forced to output mode by the parallel interface when data is to be output. In input mode the data ports can be controlled by the MSCI I/O controller registers. Data ports must be left in input mode so they can be driven by external device. 0: Input mode 1: Output mode Bit 6:4 = F[2:0] Frequency prescaler. These bits are set and cleared by software. They
select the prescaler factor for the control signal (applied to the 60 MHz clock)
F[2] F[1] F[0] Control Signal Frequency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Not allowed 30MHz 20MHz 15MHz 12MHz 10MHz 8.5MHz 7.5MHz
Bit 3 = CP Clock Polarity. This bit is set and cleared by software. 0: Falling edge clock pulse 1: Rising edge clock pulse Bit 2:0 = CSS[2:0] Control Signal Shape. These bits are set and cleared by software. They are used to select the clock edge position in the clock cycle by steps of 16.66ns and thus, control the clock duty cycle. CSS[2:0] must be lower than F[2:0] or equal to F (Frequency selection) and greater than 0. For more detailed description of the control signal generation refer to chapter "CONFIGURATION OF THE CONTROL LINE SIGNALS"
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MSCI PARALLEL INTERFACE (Cont'd) PARALLEL INTERFACE CONFIGURATION REGISTER 2 (PCR2) Read / Write Reset Value: 0000 0000 0000 0000 (0000h)
15 ED RF PID CSE7 CSE6 CSE5 8 CSE4 7 CSE3 CSE2 CSE1 CSE0 ROE ESB FSB 0 CLDV
Bit 15 = Reserved. Bit 14 = ED ECC Disable. This bit is set and cleared by software. It disables the ECC generator and forces the ECC line and column parities to reset value. 0: ECC generator enabled. 1: ECC generator disabled. Bit 13 = RF Reset FIFO.(write only) This bit is set by software and is always read as 0. Writing '1' in this bit resets the FIFO to empty. Note: this Reset FIFO command does not modify the value of the number of bytes written in the FIFO. The LBF byte will still rise after writing the expected number of bytes in the FIFO even if some were deleted by a FIFO reset. This bit must be used only to force the FIFO to empty if the FIFO is left at a non empty state at the end of a transfer. Bit 12 = PID Parallel Interface Disable. This bit is set and cleared by software. Disabling the Parallel interface stops the communication and the double buffer but does not reset the configuration registers. Note: setting the PID bit does not release the control signal output enable and does not reset the FIFO. 0: Parallel interface is enabled 1: Parallel interface is disabled Bit 11:4 = CSE[7:0] Control Signal Enable. These bits are set and cleared by software. 0: Control line output disabled (not driven by control signal generator) 1: Control line output enabled (driven by control signal generator) Bit 3 = ROE Read On Edge. This bit is set and cleared by software. This bit is only used in input mode to define when the input data has to be read. Read on edge configuration must be selected for external devices using Read enable signals. Read at end of cycle configuration must be chosen for synchronous ex-
ternal devices with data maintained on data port. 0: Read at the end of each cycle. 1: Read on the active edge of the control signal. Bit 2 = ESB ECC Swap Bytes. This bit is set and cleared by software. It selects the order of the bytes in the word when sent to the ECC generator in 16-bit mode. 0: Do not swap bytes (most significant byte first) 1: Swap bytes (least significant byte first) Bit 1 = FSB FIFO Swap Bytes. This bit is set and cleared by software. It selects the order of the bytes in the word when reading/writing from/to the FIFO. It affects both standard 16-bit access to FIFO and direct FIFO copy with LDV instruction. 0: Do not swap bytes. 1: Swap bytes. Bit 0 = CLDV Control Lines Default Value. This bit is set and cleared by software. It selects the default value that is forced on the active control lines when no pulse is generated and when communication is over or not started. When the default value is changed, it will be effective on the enabled control ports one 60 MHz clock cycle after. To avoid an unexpected pulse on the control signal, it is mandatory to change the CLDV value only when all control lines are disabled. 0: Control line default value = 0 1: Control line default value = 1 Note: Configuration registers PNDR, PCR1 and PCR2 must not be modified when a communication is on-going.
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MSCI PARALLEL INTERFACE (Cont'd) PARALLEL INTERFACE STATUS REGISTER (PSR) Read Reset Value: 0000 0000 0000 1101 (000Dh)
15 0 0 0 0 0 0 0 8 0 7 0 RDPE E2R E1R LBF EOC FF 0 FE
Bit 15:7 = Reserved Bit 6 = RDPE RS Decoder Protocol Error. This bit is set by hardware when data are sent to RS Decoder when it is not ready. MSCI must receive a soft reset to restart the RS decoder in a correct state. (Can be used for debug) 0: No RS protocol error 1: RS protocol error detected Bit 5 = E2R ECC2 ready. This bit is set by hardware when the ECC2 line parity and column parity are updated and reset by hardware when a new start is generated by writing '1' in bit 15 of the PCR1 register. 0: ECC2 not ready 1: ECC2 ready Bit 4 = E1R ECC1 ready. This bit is set by hardware when the ECC1 line parity and column parity are updated and cleared by hardware when a new start is generated by writing a 1 in bit 15 of the PCR1 register. 0: ECC1 not ready 1: ECC1 ready Bit 3 = LBF Last Byte of FIFO. In output mode, this bit is set by hardware when the total number of bytes written in the FIFO is equal to the number of bytes to be sent. In input mode it is set by hardware when the total number ECC1 LINE PARITY (ELP1) Read Reset Value: 1111 1111 1111 1111 (FFFFh)
15 LP15 LP14 LP13 LP12 LP11 LP10 LP9 8 LP8 7
of bytes read from the FIFO is equal to the expected number of bytes. In both modes, it is reset by hardware when a new start pulse is generated by writing a 1 in bit 15 of the PCR1 register. 0: Last byte of the FIFO not read/written 1: Last byte of the FIFO read/written Bit 2 = EOC End Of Communication. This bit is set by hardware when the parallel interface communication is over and reset by software when a new start is generated by writing '1' in bit 15 of the PCR1 register. 0: Communication is on going. 1: Communication is over. Bit 1 = FF FIFO full. This bit is set and cleared by hardware. 0: FIFO not full 1: FIFO full Bit 0 = FE FIFO empty. This bit is set and cleared by hardware. 0: FIFO not empty 1: FIFO empty Note: The E2R and E1R flags are not reset immediately by the start but 4 MSCI clock cycles after.
0 LP6 LP5 LP4 LP3 LP2 LP1 LP0
LP7
Bit 15:0 = LP[15:0] Line Parity. ECC1 Line parity bits These bits are set by hardware and reset when a new start is generated by writing '1' in bit 15 of the PCR1 register.
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MSCI PARALLEL INTERFACE (Cont'd) ECC1 COLUMN PARITY (ECP1) Read Reset Value: 0000 0000 1111 1111 (00FFh)
15 0 0 0 0 0 0 0 8 0 7 CP5 CP4 CP3 CP2 CP1 CP0 1 0 1
Bit 15:8 = Reserved. Bit 7:2 = CP[6:0] ECC1 Column parity. ECC1 column parity bits These bits are set by hardware and reset when a new start is generated by writing a 1 in bit 15 of the PCR1 register. Bit 1:0 = Reserved. ECC2 LINE PARITY (ELP2) Read Reset Value: 1111 1111 1111 1111 (FFFFh)
15 LP15 LP14 LP13 LP12 LP11 LP10 LP9 8 LP8 7 LP7 LP6 LP5 LP4 LP3 LP2 LP1 0 LP0
Bit 15:0 = LP[15:0] Line Parity. ECC2 line parity bits These bits are set by hardware and reset when a new start is generated by writing a 1 in bit 15 of the PCR1 register. ECC2 COLUMN PARITY (ECP2) Read Reset Value: 0000 0000 1111 1111 (00FFh)
15 0 0 0 0 0 0 0 8 0 7 CP5 CP4 CP3 CP2 CP1 CP0 1 0 1
Bit 15:8 = Reserved. Bit 7:2 = CP[6:0] ECC1 Column parity. ECC1 column parity bits These bits are set by hardware and reset when a new start is generated by writing a 1 in bit 15 of the PCR1 register.
Bit 1:0 = Reserved.
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MSCI PARALLEL INTERFACE (Cont'd) REED SOLOMON CONTROL STATUS REGISTER (RCSR) Read / Write Reset Value: 0100 0000 0000 0000 (4000h).
15 DOFF DOFE DLWR DRR DEFV DEF DEOC 8 DUE 7 DNE[2] DNE[1] DNE[0] DE EPR FD EE 0 DIFF
Bit 15 = DOFF Decoder Output FIFO Full. This bit is set by hardware when the decoder output FIFO is full and reset by hardware when MSCI software reads data from this FIFO through the RDFDR register. 0: RS Decoder output FIFO not full. 1: RS Decoder output FIFO full. Bit 14 = DOFE Decoder Output FIFO Empty. This bit is set by hardware when the 8th word is read by MSCI software from the decoder output FIFO through the RDFDR register. It is reset by hardware when FIFO is full again. 0: RS Decoder output FIFO not empty. 1: RS Decoder output FIFO empty. Bit 13 = DLWR Decoder Last Word Read. This bit is set by hardware when the last word is read from the decoder output FIFO. It is reset by hardware when a word that is not the last of a 512byte packet is read from the decoder output FIFO. 0: RS Decoder last word not read. 1: RS Decoder last word read. Bit 12 = DRR Decoder Ready to Receive. This bit is set and reset by hardware. It indicates whether the decoder is ready to be used or not. Data must not be sent to the decoder if DRR=0. refer to Section 17.8 for more information. 0: RS Decoder not ready to receive. 1: RS Decoder ready to receive. Bit 11 = DEFV Decoder Error Flag Valid. This bit is set by hardware when the error flag is valid. This happens a few MSCI cycles after the decoder received a complete packet. It is reset by hardware when the first symbol of the next data packet is received by the decoder. 0: RS Decoder error flag is valid. 1: RS Decoder error flag is not valid. Bit 10 = DEF Decoder Error Flag. This bit is set by hardware when an error is detected in the current data packet. This flag is significant only when DEFV bit is set. It is reset by hardware when the first symbol of the next data packet is received by the decoder. 0: No error detected by RS decoder.
1: Error(s) detected by RS decoder. Bit 9 = DEOC Decoder End Of Correction. This bit is set by hardware when the correction algorithm is finished and when all words of the 512byte data packet are read from the decoder output. It is reset by hardware when the first symbol of the next data packet is received by the decoder. 0: RS Decoder correction not finished. 1: RS Decoder correction finished. Bit 8 = DUE Decoder Uncorrectable Error. This bit is set by hardware when the decoder detects an error that can not be recovered. This flag is significant only when DEOC=1 (after full decoding process including the reading of the complete decoded data packet from the decoder output FIFO. It is reset by hardware when the first symbol of the next data packet is received by the decoder. 0: No uncorrectable error detected by RS decoder. 1: Uncorrectable error(s) detected by RS decoder. Bit [7:5] = DNE[2:0] Decoder Number of Errors. These bits are set by hardware by the decoder to give the number of errors detected. This flag is significant only when DEOC=1 and if the DUE flag is not set. It is reset by hardware when the first symbol of the next data packet is received by the decoder.
DNE[2] 0 0 0 0 1 1 1 1 DNE[1] 0 0 1 1 0 0 1 1 DNE[0] 0 1 0 1 0 1 0 1 Number of errors 0 1 2 3 4 N/A N/A N/A
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MSCI PARALLEL INTERFACE (Cont'd) Bit 4 = DE Decoder Enable. This bit is set and reset by software to enable or disable the RS decoder. If decoder is enabled, data sent or received by parallel interface are also sent to the decoder input. If DE is reset, data transferred with parallel interface are not taken into account by the RS decoder. 0: RS Decoder disabled 1: RS Decoder enabled Bit 3 = EPR Encoder Parity Ready. This bit is set by hardware when parity bits are ready to be read from the encoder output FIFO. It is reset by hardware when the first data of a new data packet is received by the encoder. 0: RS Encoder parity is not ready 1: RS Encoder parity is ready Bit 2 = FD Feed Decoder. (write only) Write 1 in this bit to send the content of the decoder input FIFO to the decoder. This must be done to provide parity symbols to the decoder in 10-bit format (eight 10-bit symbols are automatically sent from the decoder input FIFO to the decoder cell). The Decoder enable bit must be set before writing 1 in bit FD to have the parity symbols correctly taken into account by the RS decoder. 0: No effect 1: Send parity symbols to decoder now. Bit 1 = EE Encoder Enable. This bit is set and reset by software to enable or disable the RS encoder. When encoder is enabled, data sent or received by the parallel interface are also sent to the encoder input. If EE is reset, data transferred through the parallel interface are not taken into account by the RS encoder. 0: RS Encoder disabled. 1: RS Encoder enabled. Bit 0 = DIFF Decoder Input FIFO Full. This bit is set by hardware when the decoder input FIFO is full and reset by hardware when the content of the FIFO is sent to the Decoder. 0: Decoder input FIFO not full. 1: Decoder input FIFO full.
REED SOLOMON DECODER FIFO REGISTER (RDFR) Read / Write Reset Value: 0000 0000 0000 0000 (0000h).
15 DFD15 DFD14 DFD13 DFD12 DFD11 DFD10 DFD9 8 DFD8 7 DFD7 DFD6 DFD5 DFD4 DFD3 DFD2 DFD1 0 DFD0
Bit [15:0] = DFD Decoder FIFO Data. Writing into this register adds a word into the RS decoder input FIFO (used to send parity symbols in 10-bit format to the decoder)
Reading this register returns a 16-bit word from the RS decoder Output FIFO. If RS decoder Output FIFO is empty when read, the MSCI core is frozen until the FIFO is ready to be read.
REED SOLOMON ENCODER FIFO REGISTER (REFR) Read Reset Value: 0000 0000 0000 0000 (0000h).
15 EFD15 EFD14 EFD13 EFD12 EFD11 EFD10 EFD9 8 EFD8 7 EFD7 EFD6 EFD5 EFD4 EFD3 EFD2 EFD1 0 EFD0
Bit [15:0] = EFD Encoder FIFO Data. Reading this register returns a 16-bit word from the RS encoder Output FIFO. This FIFO contains 5 16-bit words that must all be read in order to let the FIFO pointer pointing on the first word for next
data packet. Reading this register when FIFO is not ready does NOT freeze the MSCI CPU.
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18 ELECTRICAL CHARACTERISTICS
18.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to VSS. 18.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the Devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 18.1.2 Typical values Unless otherwise specified, typical data are based on TA=25C, VDD33=3.3V. They are given only as design guidelines and are not tested. 18.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 18.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 70. Figure 70. Pin loading conditions 18.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 71. Figure 71. Pin input voltage
DEVICE PIN
VIN
DEVICE PIN
CL
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18.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the Device. This is a stress rating only and functional operation of the Device under these condi18.2.1 Voltage Characteristics
Symbol VDD33 - VSS VIN
1) & 2)
tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Ratings Supply voltage Input voltage on any other pin Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model)
Maximum value 4.0 VSS-0.3 to VDD33+0.3
Unit V V
VESD(HBM) VESD(MM)
see section 18.7.3 on page 168
18.2.2 Current Characteristics
Symbol IVDD33 IVSS Ratings Total current into VDD33 power lines (source) Total current out of VSS ground lines (sink) Output current sunk by any I/O D2 type IIO
(4) 3) 3)
Maximum value 200 200 25 35 50 -25
Unit
Output current sunk by any I/O D4 type Output current sunk by any I/O D8 type Output current source by any I/Os and control pin
mA
18.2.3 Thermal Characteristics
Symbol TSTG TJMAX Ratings Storage temperature range Maximum junction temperature 7) Value -65 to +150 120 Unit C C
Notes: 1. Directly connecting the RESET and I/O pins to VDD33 or VSS could damage the Device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD33 or VSS. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD33 while a negative injection is induced by VIN162/186
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18.3 OPERATING CONDITIONS 18.3.1 General Operating Conditions
Symbol fCPU VDD33 TA Power Supply Ambient temperature range Parameter Internal clock frequency Conditions Min 0 2.7 0 Max 30 3.6 70 Unit MHz V C
fCPU [MHz]
FUNCTIONALITY GUARANTEED IN THIS AREA
30 FUNCTIONALITY NOT GUARANTEED 15 IN THIS AREA 6 3 0 2.0 2.5 2.7 3.0 3.3 3.6
FUNCTIONALITY GUARANTEED IN THIS AREA EXCEPT USB CELL 1)2)
SUPPLY VOLTAGE [VDD33]
Notes: 1. USB2 PHY does not function under 3V. 2. Supported by low voltage devices, ST7267C8T1L and ST7267R8T1L 18.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the Device functional operating modes over temperature range does not take into account the clock source current consumption. To get the total Device consumption, the two current values must be added (except for HALT mode for which the clock is stopped). 18.4.1 RUN and WAIT Modes
Symbol Parameter PLL ON Supply current in RUN mode (see Figure 72) IDD Supply current in WAIT mode (see Figure 73) PLL ON Conditions fOSC=12MHz, fCPU=30MHz fOSC=12MHz, fCPU=15MHz Min 15 10 1) 8 7
1) 1)
Typ 25 20 14 12 20 10
Max 35 30 1) 22 1) 21 1) 30 1) 20
Unit
PLL OFF fOSC=12MHz, fCPU=6MHz PLL OFF fOSC=12MHz, fCPU=3MHz PLL ON fOSC=12MHz, fCPU=6MHz PLL OFF fOSC=12MHz, fCPU=3MHz
mA
10 1) 6
Note: 1. Not tested in production, guaranteed by characterization.
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Figure 72. Typical IDD in RUN vs. fCPU
IDD RUN vs. Vdd and fcpu
25 20 15 10
PLL ON, fcpu=30M Hz
Figure 73. Typical IDD in WAIT vs. fCPU
IDD WFI vs. VDD33
25
IDD RUN (mA)
IDD WFI (mA)
20 15 10 5 0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
PLL ON f cpu=15M Hz PLL OFF fcpu=3M Hz
5 0 2.7 2.8 2.9 3 3.1 3.2 3.3
PLL ON, fcpu=15M Hz PLL OFF, fcpu=6M Hz PLL OFF, fcpu=3M Hz
3.4
3.5
3.6
Vdd (V)
Vdd (V)
18.4.2 HALT Modes
Symbol IDD Parameter Supply current in HALT mode Conditions Regulator and PHY ON Powerdown mode
2)
Min 2 1) 60
Typ 4 120
Max 7 1) 400
Unit mA A
Notes: 1. Not tested in production, guaranteed by characterization. 2. In order to reach this value, the software must force the regulator and the PHY into powerdown mode and the IOs compensation cell off.
18.4.3 Supply and Clock Managers The previous current consumption specified for the Device functional operating modes over temperature range does not take into account the
Symbol IDD(CK) Parameter Supply current of crystal oscillator
3)
clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode).
Conditions Typ 1) 1000 Max 2) 2000 Unit A
Notes: 1. Typical data are based on TA=25C and fCPU=12MHz. 2. Data based on characterization results, not tested in production. 3. Data based on characterization results done with the external components specified in Section 18.5.2, not tested in production.
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18.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD33, fOSC, and TA. 18.5.1 General Timings
Symbol tc(INST) tv(IT) Parameter Instruction cycle time Interrupt reaction time tv(IT) = tc(INST) + 10
2)
Conditions fCPU=15MHz fCPU=12MHz
Min 2 133 10 0.666
Typ 1) 3 200
Max 12 800 22 1.466
Unit tCPU ns tCPU s
Notes: 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution.
18.5.2 Crystal Oscillator The Device internal clock is supplied from a crystal oscillator. All the information given in this paragraph are based on characterization results with specified typical external components. In the application the load capacitors have to be placed as close as possible to the oscillator pins in order to
Symbol fOSC CKACC OSC Parameter Oscillator Total crystal oscillator accuracy Crystal oscillator duty cycle 2) frequency 1)
minimize output distortion and start-up stabilization time. Refer to the crystal manufacturer for more details (frequency, package, accuracy...).
Conditions abs. value + temp + aging
Min
Typ 12
Max +/-60 55
Unit MHz ppm %
45
50
Figure 74. Typical Application with a Crystal
VDDA
CL OSCIN CRYSTAL CL OSCOUT RS 3)
Device
Notes: 1. The oscillator selection can be optimized in terms of supply current using an high quality crystal with small RS value. Refer to the crystal manufacturer characteristics for more details. 2. The crystal oscillator duty cycle has to be adjusted through the two CL capacitors. Refer to the crystal manufacturer for more details. 3. Depending on the crystal power dissipation, a serial resistor RS may be added. Refer to the crystal manufacturer for more details.
Table 36. Typical CL and RS Values by Crystal
Supplier NDK Typical Crystal AT51 or AT41 CL (pF) 16 RS () 560
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18.6 MEMORY CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. 18.6.1 RAM and Hardware Registers
Symbol VRM Parameter Data retention mode
1)
Conditions HALT mode (or RESET)
Min 1.4
Typ
Max
Unit V
Note: 1. Minimum V18_DIG supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Guaranteed by construction, not tested in production.
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18.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 18.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD33 and VSS33 through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. 18.7.1.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical applicaSymbol VFESD Parameter
tion environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: - Corrupted program counter - Unexpected reset - Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Conditions Level/ Class 4B
Voltage limits to be applied on any For TQFP64 (10x10), VDD33=3.3V, TA=+25C, fOSC=12MHz I/O pin to induce a functional disconforms to IEC 1000-4-2 turbance Fast transient voltage burst limits For TQFP64 (10x10), VDD33=3.3V, TA=+25C, fOSC=12MHz to be applied through 100pF on VDD33 and VSS33 pins to induce a conforms to IEC 1000-4-4 functional disturbance
VFFTB
4A
18.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This
Symbol Parameter Conditions VDD33=3.3V, TA=+25C, TQFP64 10x10 package conforming to SAE J 1752/3 Note: Refer to Application Note AN1709 for data on other package types.
emission test is in line with the norm SAE J 1752/ 3 which specifies the board and the loading of each pin.
Max vs. [fOSC/fCPU] 12/15MHz 12/30MHz 16 21 27 4 20 25 25 4 dBV Unit
Monitored Frequency Band 0.1MHz to 30MHz 30MHz to 130MHz 130MHz to 1GHz SAE EMI Level
SEMI
Peak level
Notes: 1. Data based on characterization results, not tested in production.
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EMC CHARACTERISTICS (Cont'd) 18.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Absolute Maximum Ratings
Symbol VESD(HBM) Ratings Electro-static discharge voltage (Human Body Model)
18.7.3.1 Electro-Static Discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22A114A/A115A standard.
Conditions TA=+25C
Maximum value 1) Unit 2000 V
Notes: 1. Data based on characterization results, not tested in production.
18.7.3.2 Static and Dynamic Latch-Up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Electrical Sensitivities
Symbol LU DLU Parameter Static latch-up class Dynamic latch-up class TA=+25C
DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181.
Conditions VDD33=3.3V, fOSC=12MHz, TA=+25C
Class 1) A A
Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard).
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18.8 I/O PORT PIN CHARACTERISTICS 18.8.1 General Characteristics Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Vhys IL IL5V RPU C(IOD2) C(IOD2) C(IOD4) C(IOD8) Parameter Input low level voltage Input high level voltage Schmitt trigger voltage hysteresis 1) Input leakage current 5V tolerant input leakage current Weak pull-up equivalent resistor 2) I/O pin capacitance 2mA drive I/O pin capacitance 2mA drive, 5V tolerant I/O pin capacitance 4mA drive I/O pin capacitance 8mA drive VSSVINVDD33, standard I/Os VSSVINVDD33 VIN=5V, 25C VIN=VSS VDD33=3.3 V 32 30 50 1.5 1.7 1.9 2.7 10 10 6 6 3.5 3.5 1 tCPU ns 75 k pF pF pF pF ns TTL ports 0.85xVDD33 400 1 10 A Conditions Min Typ Max 0.16xVDD33 Unit V mV
tf(IOD2)out Output high to low level fall time 3) tr(IOD2)out Output low to high level rise time 3) CL=50pF tr(IOD4)out Output low to high level rise time 3) Between 10% and 90% tf(IOD8)out Output high to low level fall time 3) tr(IOD8)out Output low to high level rise time 3) tw(IT)in External interrupt pulse time 4) tf(IOD4)out Output high to low level fall time 3)
Notes: 1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. 2. The RPU pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, tested in production at VDD33 max. 3. Data based on characterization results, not tested in production. 4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.
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I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 75. Typical VIL and VIH standard I/Os
Vil/Vih (V)
I/Os pullup resistance (kOhms)
Figure 76. Typical RPU vs. VDD33 with VIN=VSS
60 55 50 45 40 35 30
I/Os pullup resistance
2.5 2
Vil/Vih (V)
1.5 1 0.5 0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
2.7
2.8
2.9
3
Vdd (V)
3.1 3.2 Vdd (V)
3.3
3.4
3.5
3.6
Figure 77. Two typical Applications with unused I/O Pin
VDD33 10k
Device
UNUSED I/O PORT
10k
UNUSED I/O PORT
Device
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I/O PORT PIN CHARACTERISTICS (Cont'd) 18.8.2 Output Driving Current Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified.
Symbol Parameter Output low level voltage for a D2 I/O pin when 8 pins are sunk at same time (see Figure 78) VOL 1) Output low level voltage for a D4 I/O pin when 8 pins are sunk at same time (see Figure 79) Conditions IIO=2mA Min Max 300 Unit
IIO=4mA
400
mV
VDD33=3.3V
Output low level voltage for a D8 I/O pin when 8 pins are sunk at same time (see Figure 80 ) Output high level voltage for a D2 I/O pin when 8 pins are sourced at same time (see and Figure 81) Output high level voltage for a D4 I/O pin VDD33-VOH 2) when 8 pins are sourced at same time (see Figure 82 ) Output high level voltage for a D8 I/O pin when 8 pins are sourced at same time (see Figure 83)
IIO=8mA
500
IIO=2mA
600
IIO=4mA
600
mV
IIO=8mA
600
Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 18.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 18.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD33. True open drain I/O pins does not have VOH.
Figure 78. Typical VOL at VDD33=3.3V (I/O D2)
Vol I/Os D2 at Vdd=3.3V
140 120
Figure 79. Typical VOL at VDD33=3.3V (I/O D4)
Vol I/Os D4 at Vdd=3.3V
140 120
Vol 2mA (mV)
100 80 60 40 20 0 0 1 2 3 4
Vol 4mA (mV)
100 80 60 40 20 0 0 1 2 3 4 5 6
Iol (mA)
Iol (mA)
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Figure 80. Typical VOL at VDD33=3.3V (I/O D8)
Vol I/Os D8 at Vdd=3.3V
140 120
Figure 82. Typical VDD33-VOH vs. VDD33 (IO D4)
Vdd-Voh I/Os D4 at Vdd=3.3V
180 160 140 120 100 80 60 40 20 0 0 1 2 3 4 5 6
Vol 8mA (mV)
100 80 60 40 20 0 0 2 4 6 8 10
Voh 4mA (mV)
Iol (mA)
Ioh (mA)
Figure 81. Typical VDD33-VOH vs. VDD33 (IO D2)
Vdd-Voh I/Os D2 at Vdd=3.3V
200
Figure 83. Typical VDD33-VOH vs. VDD33 (IO D8)
Vdd-Voh I/Os D8 at Vdd=3.3V
180 160 140 120 100 80 60 40 20 0 0 2 4 6 8 10
Voh 2mA (mV)
100 50 0 0 1 2 3 4
Ioh (mA)
Voh 8mA (mV)
150
Ioh (mA)
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18.9 CONTROL PIN CHARACTERISTICS 18.9.1 Asynchronous RESET Pin TA = 0 to +55C unless otherwise specified
Symbol VIL VIH Vhys RON teh(RSTL) tg(RSTL) tew(RSTL) tiw(RSTL) Parameter Input low level voltage
1)
Conditions
Min 0.85xVDD33
Typ
Max 0.16xVDD33
Unit V mV
Input high level voltage Schmitt trigger voltage hysteresis1) Pull-up equivalent resistor External reset pulse hold time 2) Filtered glitch duration 3) External reset pulse duration Internal reset pulse duration
4)
450 VDD33=3.3V VDD33=2V 2.5 200 500 2 20 40 100 80
k s ns s Tcpu
Notes: 1. The user must ensure that the level on the RESET pin can go below the VIL max. level specified in Section 18.9.1. Otherwise the reset will not be taken into account internally. 2. To guarantee the reset of the Device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below teh(RSTL) can be ignored. Not tested in production, guaranted by design. 3. The reset network protects the device against parasitic resets. 4. The user must ensure that external reset duration respect this timing to guarantee a correct start-up of the internal regulator at power-up. Not tested in production, guaranted by design.
Figure 84. Typical RON on RESET pin
NRESET pullup (kOhms)
100
NRESET pullup (kOhms)
90 80 70 60 50 40 2 2.5 3 3.5
Vdd (V)
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18.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). 18.10.1 Watchdog Timer
Symbol Parameter Conditions Min 101 372 fCPU = 3MHz tw(WDG) Watchdog time-out duration fCPU = 6MHz fCPU = 15MHz fCPU = 30MHz 33.79 16.896 6.758 3.379 Typ Max 6 487 808 2162.58 1081.32 432.54 216.24 ms Unit tCPU
18.10.2 Time Base Unit Timer
Symbol Parameter Conditions Standalone mode fCPU = 3MHz tw(TBU) TBU time-out duration fCPU = 6MHz fCPU = 15MHz fCPU = 30MHz Min 2 0.666 0.333 0.133 0.066 Typ Max 262144 87380 43691 17477 8737 us Unit tCPU
18.10.3 16-Bit Timer
Symbol Parameter Conditions Min 1 2 fCPU = 3MHz tres(PWM) PWM resolution time fCPU = 6MHz fCPU = 15MHz fCPU = 30MHz fEXT fPWM Timer external clock frequency PWM repetition rate 666.67 333.33 133.33 66.67 0 0 fCPU/4 fCPU/4 16 MHz MHz bit ns Typ Max Unit tCPU tCPU
tw(ICAP)in Input capture pulse time
ResPWM PWM resolution
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18.11 OTHER COMMUNICATION INTERFACE CHARACTERISTICS 18.11.1 MSCI Parallel Interface
Figure 85. Timing diagrams for input mode (with max load on CTRL signal=50pf)
CTRL
external
DATA
ext device
DATA(i)
DATA(i+1)
tDS tDS is the setup time for data sampling
Figure 86. Timing diagrams for output mode (with max CTRL signal=50pf, DATA)
CTRL
external
DATA
external
DATA(i)
DATA(i+1)
tDO tDO is the data output time for data sampling
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Table 37. MSCI Parallel Interface: DC Characteristics
MSCI DC Electrical Characteristics Parameter Data Setup Time Data Output time CTRL line capacitance Data line capacitance Symbol tDS tDO Cctrl Cdata Conditions Min. Typ 1) 11 6 50 50 Max. Unit ns ns pF pF
Notes: 1. Data based on design simulation and not tested in production.
18.11.2 USB (Universal Bus Interface) Table 38. USB Interface: DC Characteristics
USB DC Electrical Characteristics Symbol Parameter Conditions VDD33=3.3V, regulator and PHY ON IDDsuspend Suspend current VDD33=3.3V, Powerdown mode, 25C 2) Pull-up resistor 1) 60 90 1.5 190 uA k Min. 0.5 1) Typ. 1.5 Max. 6 1) Unit mA
RPU
Full Speed Mode VTERM VOH VOL VCRS Termination Voltage High Level Output Voltage Low Level Output Voltage Crossover Voltage 1.3 0.8 2.8 2.0 3.6 0.8 2.0 V V V V
High Speed Mode VHSOH VHSOL HS Data Signalling High HS Data Signalling Low 400 5 mV mV
Notes: 1. Not tested in production, guaranteed by characterization. 2. In order to reach this value, the software must force the regulator into powerdown mode and the IOs compensation cell off.
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Table 39. USB Interface: Timing
USB DC Electrical Characteristics Symbol Full Speed Mode TFR TFF Rise Time Fall Time CL=50pF CL=50pF 4 4 20 20 ns ns Parameter Conditions Min. Max. Unit
High Speed Mode THSR THSF THSDRAT Rise Time Fall Time HS Data Rate 479.76 500 1) 500
1)
ps ps Mb/s
480.24
Notes: 1. Not tested in production, guaranteed by characterization.
Table 40. USB High Speed Transmit Waveform requirements
Voltage Level (DP - DN) Unit Interval (UI) Level 1 Level 2 Point 1 Point 2 Point 3 Point 4 Point 5 Point 6 475 mV -475 mV 0V 0V 300 mV 300 mV -300 mV -300 mV Time 2.082 to 2.084 ns 5% UI 95% UI 35% UI 65% UI 35% UI 65% UI
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18.11.3 SPI - Serial Peripheral Interface Subject to general operating condition for VDD, fCPU, and TA unless otherwise specified.
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(SS) th(SS) tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO) tv(SO) th(SO) tv(MO) th(MO) Parameter
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
Conditions Min fCPU/64 0.0937 0 Max fCPU/2 3 fCPU/2 3 Unit
Master SPI clock frequency fCPU=6MHz Slave fCPU=6MHz SPI clock rise and fall time SS setup time SS hold time SCK high and low time Data input setup time Data input hold time Data output access time Data output disable time Data output valid time Data output hold time Data output valid time Data output hold time Slave Slave Master Slave Master Slave Master Slave Slave Slave Slave (after enable edge) Master (before capture edge)
MHz
see I/O port pin description 160 160 130 120 130 130 130 130 0 160 320 160 0 0.25 0.25 tCPU
ns
Figure 87. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) MISO OUTPUT tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
see note 2
see note 2
MSB OUT
BIT6 OUT
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Notes: 1. Data based on design simulation, not tested in production. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 3. Measurement points are done at CMOS levels: 0.3xVDD33 and 0.7xVDD33.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) Figure 88. SPI Slave Timing Diagram with CPHA=11)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
MISO OUTPUT
see note 2
HZ
MSB OUT
BIT6 OUT
see note 2
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Figure 89. SPI Master Timing Diagram 1)
SS INPUT tc(SCK) CPHA=0 CPOL=0 SCK INPUT CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT tv(MO) th(MI) tr(SCK) tf(SCK)
MSB IN
BIT6 IN
LSB IN
th(MO)
MOSI OUTPUT
see note 2
MSB OUT
BIT6 OUT
LSB OUT
see note 2
Notes: 1. Measurement points are done at CMOS levels: 0.3xVDD33 and 0.7xVDD33. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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19 PACKAGE CHARACTERISTICS
19.1 PACKAGE MECHANICAL DATA In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to solderFigure 90. 48-Pin Thin Quad Flat Package
mm Min 0.05 1.35 0.17 0.09 9.00 7.00 9.00 7.00 0.50 0 0.45 3.5 0.60 1.00 48 7 0 1.40 0.22 Typ Max 1.60 0.15 0.002 Min inches Typ Max 0.063 0.006
ing conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com, with specific Application Notes covering the main technical aspects related to lead-free conversion (AN2033, AN2034, AN2035 and AN2036).
Dim.
D D1 A1 b A A2
A A1 A2 b C D D1 E E1 e L L1 N
1.45 0.053 0.055 0.057 0.27 0.007 0.009 0.011 0.20 0.004 0.354 0.276 0.354 0.276 0.020 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008
E1
E
e
L1 L
c
Number of Pins
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Figure 91. 64-Pin Thin Quad Flat Package (10 x10)
Dim.
D D1 A1 A A2
mm Min 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 64 7 0 1.40 0.22 Typ Max 1.60 0.15 0.002 Min
inches Typ Max 0.063 0.006
A A1 A2 b
1.45 0.053 0.055 0.057 0.27 0.007 0.009 0.011 0.20 0.004 0.472 0.394 0.472 0.394 0.020 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008
b
c D D1
E1
E e
E E1 e
c
L L1 N
L1
L
Number of Pins
19.2 THERMAL CHARACTERISTICS
Symbol RthJA PD Ratings Package thermal resistance (junction to ambient) TQFP48 TQFP64 Power dissipation 1) Value 70 55 400 Unit C/W mW
Notes: 1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the Device internal power (IDDxVDD) and PPORT is the port power dissipation determined by the user.
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20 DEVICE CONFIGURATION AND ORDERING INFORMATION
20.1 OPTION BYTE The option byte allows the hardware configuration of the microcontroller to be selected. In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list).
7 WDGHWR
0 -
OPT1 = WDGHWR Hardware Watchdog Reset This option permanently enables the watchdog reset. 0: Hardware Watchdog is disabled (watchdog to be enabled by software). 1: Hardware Watchdog is activated (watchdog always enabled) .
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21 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents and the list of the selected options (if any). The ROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
Figure 92. ROM Factory-Programmed Device Types Family (ROM, FLASH, FASTROM) Number of pins ROM size Package Temperature Range Low Voltage ROM Code (three letters)
ST 7267 R 8 T 1 L / xxx
L = Low Voltage (2.7 - 3.6 V) No letter = Standard (3.0 - 3.6 V)
0= 25C 1= Standard (0 to +70C)
T=Thin Quad Flat Pack
8=54K
R = 64 pins (TQFP64 10x10) C=48 pins (TQFP48 7x7)
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DEVICE OPTION LIST ST7267
Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................................................................ Contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. STMicroelectronics references: Device Type/Memory Size/Package (check only one option): ----------------------------------------------------------------------------------------------| ROM DEVICE: | STANDARD VOLTAGE | LOW VOLTAGE | ----------------------------------------------------------------------------------------------| TQFP48: | [ ] ST7267C8T1 | [ ] ST7267C8T1L | | TQFP64: | [ ] ST7267R8T1 | [ ] ST7267R8T1L | ----------------------------------------------------------------------------------------------Conditioning (check only one option): Packaged Product | Die Product (dice tested at 25C only) ----------------------------------------------------------------------------------------------[ ] Tape & Reel | [ ] Sawn wafer on sticky foil [ ] Tray | Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _" Authorized characters are letters, digits, '.', '-', '/' and spaces only. For marking, two lines are possible with a maximum of 8 characters per line. Watchdog Reset: WDGHWR [ ] Software activation [ ] Hardware activation Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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22 REVISION HISTORY
Table 41. Revision History
Date 4-Oct-2005 Revision 1 First Release Description of Changes
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Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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